How to understand "Coherency" bit in "Extended Capability Register"?
I am studying "Intel ® Virtualization Technology for Directed I/O" document now. In "Register Descriptions" section, I find there is a "Coherency" bit in "Extended Capability Register". The document describes this bit like this:
This field indicates if hardware access to the root, context, page-table and interrupt-remap structures are coherent (snooped) or not.
Could anyone give an explanation about how to understand "hardware access to ... are coherent(snooped)" here? If possible, give an example is better.