Memory ordering and CLI instruction

[jmking1]

I couldn't find definitive information on this in the Intel manuals: what are the semantics of memory orderings with respect to the CLI instruction? Is CLI a full memory barrier, is it a full serializing instruction, is it some sort of partial barrier, or is it no barrier at all? Intuition would tell me that it's a full memory barrier, but the docs don't say anything about it. I know x86 enforces "processor order" for loads and stores, which is almost completely consistent, but how does CLI interact with that scheme?

Are there any other documents that talk about this sort of thing in great detail?

Thanks.

[Intel_Software_Netw1]

We will forward your question to our engineering contacts and let you know how they respond.

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

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[Intel_Software_Netw1]

Our engineering contacts are not certain that they understand the precise nature of your question. They responded:

CLI sets the IF bit in the EFLAGS register to 0. There is no memory operation, so it is not a memory barrier of any sort. Is there any chance you meant to ask about the CLFLUSH instruction instead (which is ordered only by MFENCE)? CLI is definitely a slower instruction.

Also, if you can let us know exactly what you are trying to do with the instruction, we may be able to provide more information.

Regards,

Lexi S.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

[jmking1]

I was having a discussion with a coworker on the "speed" of the CLI instruction, meaning how it affects the rest of the instructions in flight in the processor. For example:

cli
cmp $0, some_variable
je end
movl $0xFF, some_other_variable
end:
sti

Does the processor speculatively execute the instructions between the cli and the sti, or does it wait until the cli is retired (architecturally visible) before executing those instructions, especially the load and store? And is it even necessary (for correctness) that the cli instruction be retired before performing the load and store?

In summary: is CLI a "slow" instruction, in that it causes basically a pipeline flush before executing any subsequent instructions? If it is not, how does the processor ensure correctness, especially for memory operations?

[Intel_Software_Netw1]

Our engineering contacts are still investigating your issue. Thank you for your patience.

Regards,

Jim A.

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

[Intel_Software_Netw1]

Hello,

CLI is not necessarily a serializing instruction.If aninstruction *after* CLI needs the value of EFLAGS.IF (there are only a few of these) then while the CLI is still in flight,the above instructionwill stall until theCLI has retired.

The code below does not look likeit will run into this problem (sterilization).

cli
cmp $0, some_variable
je end
movl $0xFF, some_other_variable
end:
sti

I hope this helps.

Best regards,

Jim A

IntelSoftware NetworkSupport

http://www.intel.com/software

Contact us

Message Edited by intel.software.network.support on 01-31-2006 11:26 AM