P4 / Xeon 's L2 cacheline size

[bigbearking]

HI,

I am writing a paper and I need to describe my experimental environment. I know it's a P4/ Xeon 2.4 GHZ with 400Mhz frontside bus. I believe L1 cacheline is 64 bytes and L2 cacheline is 128 bytes. However, psinv command in perfsuite tells me L2 cacheline is 64 bytes. I tried a micro benchmark called calibrator, and it told me L1 cacheline is 32 bytes and L2 is 128 bytes.

I guess I can't believe either of them. I want to make sure that all the P4 models have 64-byte L1 cache lines and 128-byte L2 cache lines.

Thanks a lot!

[TimP]

Cache line is 64 bytes. The "second (alternate) sector prefetch" feature causes reads to bring pairs of cache lines into L2, giving some of the effects of doubling cache line size. This would be in effect on your P4, or any model without a BIOS feature deselection. Writes will access only single cache lines.

[bigbearking]

Thanks a lot for you quick answer. Can you point to me where to find this information in case I need to cite the source?

[manhattan95]

Try cpu-z : http://www.cpuid.org/cpuz.php