Software Archive
Read-only legacy content
Announcements
FPGA community forums and blogs have moved to the Altera Community. Existing Intel Community members can sign in with their current credentials.
17060 Discussions

Page faults VM exits: PTE A and D bits

hellfire
New Contributor I
948 Views
Are A and D bits in the corresponding PTE and A bit in the PDE updated when page fault VM exit occurs? Or VM should do this manually when emulating opcode?
0 Kudos
1 Solution
David_O_Intel1
Employee
948 Views
The A and D bits in a PTE are not updated for an instruction that causes a page fault (regardless of whether the page fault causes a VM exit).

The A bit in a PDE may or may not be updated for an instruction that causes a page fault. It is implementation-specific. (Of course, the A bit in PDE may have been set earlier by an access using a different PTE that did not cause a fault.)

Thus, if a VMM handles a page fault by emulating the faulting instruction, it may need to update these bits manually.

David Ott

View solution in original post

0 Kudos
1 Reply
David_O_Intel1
Employee
949 Views
The A and D bits in a PTE are not updated for an instruction that causes a page fault (regardless of whether the page fault causes a VM exit).

The A bit in a PDE may or may not be updated for an instruction that causes a page fault. It is implementation-specific. (Of course, the A bit in PDE may have been set earlier by an access using a different PTE that did not cause a fault.)

Thus, if a VMM handles a page fault by emulating the faulting instruction, it may need to update these bits manually.

David Ott
0 Kudos
Reply