Repost: The delay of voltage/frequency scaling

[Zhiquan_Lai]

Dear all, 

I'm reading the MPSS3.3 source codes.

In \drivers\micpm\mic_cpufreq.c, there are some definitions as following:

1	#define K1OM_FREQ_DELAY    10    /* delay this many usecs, for each loop of the freq set routine */

2	#define K1OM_VID_DELAY    50    /* delay this many usecs for each loop of the vid set routine   */

3	#define K1OM_FREQ_LOOPS    50    /*  # of times to loop before we bail                           */

4	#define K1OM_VID_LOOPS    2

By checking the routines of set_cur_freq_k1om() and set_vid_k1om(), where the above definitions are used to control the frequency/voltage scaling, I guess that maximal delay of frequency scaling is 10x50=500 usecs, while it's 50x2x2=200 usecs for voltage scaling.

Am I right?

And my question is why the voltage scaling takes shorter than frequency scaling. Usually, the voltage scaling takes much longer.

Is there any documents where I can find some information about the delay of frequency/voltage scaling?

Thanks a lot.

Zhiquan

[Loc_N_Intel]

Hi Zhiquan,

The document https://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-system-software-developers-guide discusses about power management and also in the blog https://software.intel.com/en-us/forums/topic/304011

However, none of them talks about the delay of voltage and frequency scaling. Let me bring your question to developers here. I will get back to you as soon as I have an answer.

Thank you.

[TaylorIoTKidd]

I am trying to find some more specific information. I'll let you know what I find.

Regards
--
Taylor
 

[Zhiquan_Lai]

Dear Taylor and Loc,

So glad to receive your comments.

Looking forward to hear from you for further information.

Best regards,

Zhiquan

[Loc_N_Intel]

Hi Zhiquan,

First of all, what you guess from the file mic_cpufreq.c is correct: the maximal frequency scaling delay is 500 usecs and the maximal voltage scaling delay is 200 usecs.

Here is the information from developers that both Taylor and I got:

"With regards to the maximum frequency scaling delay, it should be 1000 us, and voltage scaling should be 100 us.  When the frequency has to be switched from something under 800MHz  to something over 800MHz, there is a need to switch it to 800MHz first and then switch to the higher frequency. In this case, the maximum delay is 1000us, if not its 500us.  The maximum voltage scaling delay is 200us like you said.

With regards to why these values were chosen, the best answer would be that they were based on experiments conducted on emulation and real hardware with regards to the worst case length of time it takes to change the frequency and voltage".

So far, we haven't found any other documentation on this topic.

Hope this help. Thank you.

[TaylorIoTKidd]

I usually find that in any complex design, there is a common sequence that almost all designers follow:

1. Design
2. Do theoretical studies to estimate the values of various components
3. Build, test and find it doesn't work
4. Tweak values until it does

Even the best designs don't survive contact with reality unscathed.

Regards
--
Taylor