I will oversimplify, to avoid overstepping my limited expertise:
Within a single CPU package, the internal logic has the responsibility of keeping time stamp counters synchronized. This restricts freedom of individual components to do power saving state changes.
With multiple CPU packages on the same motherboard, the chip set logic has a similar responsibility, but there may be future platforms which don't take care of this.
New power management features require a means of making time stamp counting continuous across routine state changes, but I don't think there is any simplified generalization to tell which state changes will break it.
If your requirements are more exacting, the details probably exceed what can be discussed here, and may involve going through your account representative.
