Clks busy with Page Miss Handler on PMC 0x08 and 0x49

[perfwise]

Hi,

I'm measuring average page miss latency using PMCs 0x08 and 0x49. The documentation of these is here:

http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html

http://software.intel.com/sites/products/documentation/hpc/amplifierxe/en-us/lin/ug_docs/reference/index.htm#snb/events/about_front_end_performance_tuning_events.html

My question is is the cycles which the PMH is busy in PMC 0x08 due to only those generated by loads?

My next question is the counterpart for PMC 0x49, do the cycles counted there while the PMH is busy pertain only to stores?

It's vague at present, implying its for both, but all other unit masks measure only counts generated by their respective memory operation (load or store depending upon the PMC).

Thanks for any clarification

perfwise

[Patrick_F_Intel1]

Hello Perfwise,
Yes, DTLB_LOAD_MISSES.* (PMC 0x8) is just for loads.
And DTLB_STORE_MISSES.* (PMC 0x49) is just for stores.
Pat