DDR2 & DDR3 timings similarities

[CyrIng]

Hello, So far, based on X58, P35, P965 chipsets datasheets, I'm programming functions to display DRAM timings in a generic way. X58 being the reference, I can query PCI up to {sr,dr,dd}RtoR RtoW WtoR WtoW DDR3 timings ... and values match the BIOS. With P35, SameRank(sr), DifferentRank(dr), DifferentDimm(dd) definitions are named differently but explanation looks similar. The question is: can I consider an equal meaning between these fields ? For example, (X58) tddWrTWr = (P35) tWR_WR_DR // X58 Nehalem registers typedef union { // Device: 4, 5, 6 - Function: 0 - Offset: 80h unsigned int value; struct { unsigned int tsrRdTRd : 1-0, tdrRdTRd : 4-1, tddRdTRd : 7-4, tsrRdTWr : 11-7, tdrRdTWr : 15-11, tddRdTWr : 19-15, tsrWrTRd : 23-19, tdrWrTRd : 26-23, tddWrTRd : 29-26, ReservedBits : 32-29; }; } X58_MC_RANK_TIMING_A; typedef union { // Device: 4, 5, 6 - Function: 0 - Offset: 84h unsigned int value; struct { unsigned int tFAW : 6-0, tRRD : 9-6, tsrWrTWr : 10-9, tdrWrTWr : 13-10, tddWrTWr : 16-13, B2B : 21-16, ReservedBits : 32-21; }; } X58_MC_RANK_TIMING_B; //--------- // P35 registers typedef union { // Offset Channel0: 256h & Channel1: 656h unsigned short value; struct { unsigned short tRD_WR : 4-0, tWR_WR_DR : 8-4, tWR_WR_SR : 12-8, tRCD_WR : 16-12; }; } P35_MC_CYCTRK_WR; typedef union { // Offset Channel0: 258h & Channel1: 658h unsigned int value; struct { unsigned int tRD_RD_DR : 4-0, tRD_RD_SR : 8-4, tWR_RD : 12-8, tWTR : 17-12, tRCD_RD : 21-17, ReservedBits : 24-21, tREF : 32-24; // Offset 25Bh }; } P35_MC_CYCTRK_RD; See complete structures @ https://github.com/cyring/CoreFreq/blob/master/intelmsr.h CyrIng

[McCalpinJohn]

This is not going to be an easy project!  

The DDR2 and DDR3 specs have a lot of similarities, but there are a few differences.  If you register at the JEDEC web site, you can download the specifications, but I have typically found the white papers at Micron to be easier to read.  They might even have a specific document to help DDR2 designers understand the differences with introduced in DDR3.

The harder part will be understanding the topic deeply enough to identify when Intel changes the way timings are specified. Intel's documents are typically written for full-time designers, and are also typically backed by NDA documents that go into more detail. 

You will probably have the best success if you can combine reading the documents with experimentation -- trying DIMMs with different SPD values and trying different numbers of DIMMs installed and see how this changes the visible register values.   Unfortunately on the Xeon E5 v1/v2/v3/v4 processors that I work with, many/most of the interesting DRAM configuration bits (as described in Volume 2 of the processor datasheets) are only visible to the BIOS (or SMM).  Since I don't have access at that level, I have not spent much time trying to understand the configuration bits.

[CyrIng]

Thank you John for your advices. I also think it won't be easy b/c I will program based on specs and without having most hardware to test with. Beside standard timings, I would rather specialize display for the advanced ones and try to find a commun denominator in the output list count. (however let me know which ones your were looking for, if I get a chance to collect those registers.) Indeed Micron provides best available documents to understand DRAM timings. Regards CyrIng

[CyrIng]

Hello

I'm trying to gather in datasheets info from all generations but what I can't easily get are the offsets and bits structure of standard timings (tCL-tRCD-tRP-tRAS)

Paradoxically, recent processors are well documented in datasheets :
- "6th Generation for U/Y-Platforms" at offset 4C70h with tCL in [20:16] 
- "4th Generation Desktop" at offset 4c14h with tCL in [4:0] 
- X58 (already implemented) 

whereas documentation for previous gen. are lacking such usual timings.

Off course cheating in other source codes, reveals undocumented IMC register (but I want to master the data I'm coding)
- at 4000h (for SandyBdrige) 
- at 4014h (for Haswell)

At first, I though about nda, but why most Xeon(s) are publicly documented with lot of details ? 
Is there a common algorithm I'm missing to decode mainstream Core generation ? 

Regards

[McCalpinJohn · Accepted solution]

You may be able to find information about the Core i7 configuration bits by looking in the Xeon E3 datasheets.

For example, for the Sandy Bridge generation, the "Intel Xeon Processor E3-1200 Family Datasheet, Volume 2 (document 324971) (I have revision 002 from June 2011), describes the DDR timing parameters in a bunch of registers starting at offset 4000h.   This is in Section 2.13 of my version, but newer versions of the document might have shifted things around a bit.

Fewer of the registers in the bottom part of this address range are documented in the Haswell generation ("Intel Xeon Processor E3-1200 v3 Product Family Datasheet -- Volume 2 of 2" (document 329000, revision 001, June 2013), but there might be later revisions with more details.... (or the values may be the same as on the earlier generations -- if you have access it should be easy to check at least some of the fields.)

[CyrIng]

What a shock ! Structures are indeed better documented in Xeon specs, even concerning mainstream platforms. Thank you for these pointers.