The DRAM_DATA_READS/DRAM_DATA_WRITES counters are for the Haswell client/desktop/single-socket processors and are not present on the Haswell server, two socket processors.
Below is a link for documentation of uncore performance counters for Xeon:
Referencing the original link:
I cut-and paste the text below. There's nothing in that post that would lead one to conclude that the DRAM_DATA_READS and DRAM_DATA_WRITES counters are only available on Haswell single socket. In fact, one would reasonably conclude from the opening paragraph that these counters are available on Sandy Bridge and Ivy Bridge.
The web page that you are linking to is describing the memory controller performance monitoring on the single-socket "client" processors only. The dual-socket server processors have a completely different uncore with completely different performance monitoring features.
For your Ivy Bridge system, the document you want is "Intel Xeon Processor E5 v2 and E7 v2 Product Families Uncore Performance Monitoring Reference Manual". This is document number 329468, and it looks like the latest revision is 002, from February 2014.
For the Xeon E5-26xx v2 (Ivy Bridge), you can ignore references to "MC1" (Memory Controller 1), which is only present on the Xeon E7. For the Xeon E5, all four of the channels should be connected to MC0. Everything you need for the memory controller counters is in Section 2.5 of that manual.