The current Intel Xeon 6 processor architecture supports CXL type 3 devices for memory expansion. This allows to add additional memory to the native DRAM DIMMs. By default, the additional memory is exposed to the operating system as a separate NUMA node without cores assigned. OS and applications then manage the data placement based on the proximity information provided by the ACPI tables to the operating system:
# numactl -H
available: 4 nodes (0-3)
node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257
node 0 size: 2063868 MB
node 0 free: 2027289 MB
node 1 cpus: 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343
node 1 size: 2063898 MB
node 1 free: 2027387 MB
node 2 cpus:
node 2 size: 2097152 MB
node 2 free: 2097152 MB
node 3 cpus:
node 3 size: 2097152 MB
node 3 free: 2097152 MB
node distances:
node 0 1 2 3
0: 10 21 14 24
1: 21 10 24 14
2: 14 24 10 26
3: 24 14 26 10 In this example, the system has two processors, each with 2TB native memory and 2TB CXL memory. The native memory is listed in the same NUMA nodes as the respective cores. (Sub-NUMA Cluster SNC has been disabled for this test.) NUMA nodes 2 and 3, the CXL memory, have no cores associated. However, the proximity of NUMA node 2 to node 0 is only 14, while the proximity to node 1 is larger with 24, because this CXL memory is attached to socket 0. Likewise, NUMA node 3 is closer to NUMA node 1, as this CXL memory is attached to socket 1.
A unique feature of Intel Xeon processors is the ability to manage the data movement between near native memory and far CXL memory in hardware, completely transparent to the software. This feature is called Intel Flat Memory Mode. Details on the implementation, benefits and requirements can be found in this Usenix article on Managing Memory Tiers with CXL in Virtualized Environments. Once Intel Flat Memory Mode is enabled in the BIOS, the same capacity of native and CXL memory is combined into a single NUMA node:
# numactl -H
available: 4 nodes (0-3)
node 0 cpus: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257
node 0 size: 4126234 MB
node 0 free: 4120194 MB
node 1 cpus: 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343
node 1 size: 4128280 MB
node 1 free: 4123357 MB
node distances:
node 0 1
0: 10 23
1: 23 10Hardware is now managing for each cache line (64 Bytes), if it is located in native memory (also called “near memory”) or CXL memory (also called “far memory”) and the memory looks completely uniform to software. The two types of memory, native DRAM and CXL memory, are then exposed as a uniform physical memory. The addresses are directly mapped, i.e. there are always two cache lines that correspond to each other, where if one cache line is located in native DRAM, the other cache line has to be located in CXL memory:
If a cache line is accessed that is located in native memory, this cache lines is directly returned:
This is called a “near memory hit”. On the other hand, the case that a cache line is accessed that is located in CXL memory is called a “near memory miss”:
The two cache lines are then swapped between CXL memory and native DRAM and the cache line that was originally in CXL memory is returned:
While this mechanism is implemented in hardware and completely transparent to software, one might still be interested in measuring how often memory is accessed in near memory vs. far memory. This can be observed with the tool “pcm-memory” in the package Intel® Performance Counter Monitor (Intel® PCM):
As shown in the screenshot, the “near memory” (NM) hits and misses, as well as the near-memory hit rate are printed for each socket. They report how often a memory request is serviced from native DRAM vs. CXL memory. In this typical example, for most of the memory request (96%) on socket 0 the cache lines are found in native DRAM. As a consequence, the native DRAM traffic on the 8 memory channels is by a order of magnitude larger than the traffic on the 4 CXL memory devices.
Next, let’s look at a corner case where the near memory miss rate is artificially high. By allocating all memory and sequentially reading all of it, the cache lines are regularly evicted from native DRAM:
In such artificial a worst-case scenarios, the near-memory hit rate is very low and the CXL bandwidth is getting comparatively high.
Finally, let’s consider the case that the memory footprint fits totally in native DRAM. In such situations, it can happen that 100% of the memory accesses are in native DRAM:
The CXL traffic is then 0 despite the fact that native DRAM shows high bandwidth on both sockets.
As noted before, the near-memory hit rate tends to be high for the vast majority of workloads, but in case of doubt, you now have the possibility to quickly measure it on your system using pcm-memory.
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