These values clearly show

PAgra · ‎01-05-2016

Hello all,

I wish you a Happy New Year 2016.

We are facing a problem on an IBM server x3250M5 powered with a processor, which characteristics are given below.

Sometimes the kernel is crashing and we then enter a crashdump mechanism to dump the memory. At the middle of the process, the NMI handler is activated by an "unknown"NMI, which lead to reset the machine, letting the crashdump incomplete.

I already tried to figure out what could be the source of this NMI by:

- disabling the NMI watchdog.

- disabling the PERF-related CONFIG_ options in the kernel

Is this enough to be sure that this unknown NMI is not coming from any PMU counters ?

Is there a way to disable the NMI generation from those counters ?

Thanks in advance.

Best regards,

Patrick Agrain

=====================================

[root@x3250-m5 tmpd]# cat /proc/cpuinfo
processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 60
model name      : Intel(R) Pentium(R) CPU G3220 @ 3.00GHz
stepping        : 3
cpu MHz         : 2993.047
cache size      : 3072 KB
physical id     : 0
siblings        : 1
core id         : 0
cpu cores       : 1
apicid          : 0
initial apicid : 0
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx pdpe1gb rdtscp lm constant_tsc up arch_perfmon pebs bts xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm sse4_1 sse4_2 movbe popcnt xsave rdrand lahf_lm abm arat epb xsaveopt pln pts dts tpr_shadow vnmi flexpriority ept vpid fsgsbase erms
bogomips        : 5986.09
clflush size    : 64
cache_alignment : 64
address sizes   : 39 bits physical, 48 bits virtual
power management:

McCalpinJohn · ‎01-05-2016

The performance counters in the processor cores can generate interrupts depending on the settings of the fixed-function performance counters control register IA32_FIXED_CTR_CTRL (MSR 0x38D) and on the settings of each of the programmable performance counter control registers PERFEVT_SEL* (MSRs 0x186-0x189, and maybe MSRs 0x18A-0x18D, depending on the processor and configuration).

This processor model also includes MSR-based uncore performance monitors that are able to generate PMIs. These features are described in section 18.10.6 (and the places that section points to) in Volume 3 of the Intel Architecture SW Developer's Manual.

PAgra · ‎01-11-2016

Hello John,

Sorry for the late answer, but my computer was just replaced (and it required some times to get it working again...)

Thank you for your comment concerning my request. I will check the content of the mentionned MSR registers to get sure.

Best regards,

Patrick Agrain

PAgra · ‎02-26-2016

Hi all,

For informational purpose, here is the output of a modified 'inteltool' to get the value of the MSR registers.
It seems that all the MSR mentionned by M. McCalpin are set to 0.
From Vol. 3C of the Intel's SDM, may I conclude that none of the perf event counter is active ?

Therefore, may I suppose that this is not the source of the NMI ?

Best regards,
Patrick Agrain

[root@lenovo_m5 tmpd]# ./inteltool -M
CPU: ID 0x306c3, Processor Type 0x0, Family 0x6, Model 0x3c, Stepping 0x3
Northbridge: 8086:0c00 (4th generation (Haswell family) Core Processor (Desktop))
Southbridge: 8086:8c56 (C226 Series Chipset Family LPC Controller)

===================== SHARED MSRs (All Cores) =====================
MSR 0x00000017 = 0x00040000:0x00000000 (IA32_PLATFORM_ID)
MSR 0x000000CE = 0x00080838:0xF3011C00 (MSR_PLATFORM_INFO)
MSR 0x00000198 = 0x00002358:0x00001C00 (IA32_PERF_STATUS)
MSR 0x000001A2 = 0x00000000:0x00641400 (MSR_TEMPERATURE_TARGET)
MSR 0x000001AA = 0x00000000:0x00400000 (MSR_MISC_PWR_MGMT)
MSR 0x000001AD = 0x00000000:0x1C1C1C1C (MSR_TURBO_RATIO_LIMIT)
MSR 0x000001B0 = 0x00000000:0x00000000 (IA32_ENERGY_PERF_BIAS)
MSR 0x000001B1 = 0x00000000:0x88420800 (IA32_PACKAGE_THERM_STATUS)
MSR 0x000001B2 = 0x00000000:0x01000003 (IA32_PACKAGE_THERM_INTERRUPT)
MSR 0x000001FC = 0x00000000:0x0004005F (MSR_POWER_CTL)
MSR 0x00000283 = 0x00000000:0x40000001 (IA32_MC4_CTL2)
MSR 0x00000391 = 0x00000000:0x00000000 (MSR_UNC_PERF_GLOBAL_CTRL)
MSR 0x00000392 = 0x00000000:0x00000000 (MSR_UNC_PERF_GLOBAL_STATUS)
MSR 0x00000394 = 0x00000000:0x00000000 (MSR_UNC_PERF_FIXED_CTRL)
MSR 0x00000395 = 0x00000000:0x00000000 (MSR_UNC_PERF_FIXED_CTR)
MSR 0x00000396 = 0x00000000:0x00000003 (MSR_UNC_CBO_CONFIG)
MSR 0x000003B0 = 0x00000000:0x00000000 (MSR_UNC_ARB_PERFCTR0)
MSR 0x000003B1 = 0x00000000:0x00000000 (MSR_UNC_ARB_PERFCTR1)
MSR 0x000003B2 = 0x00000000:0x00000000 (MSR_UNC_ARB_PERFEVTSEL0)
MSR 0x000003B3 = 0x00000000:0x00000000 (MSR_UNC_ARB_PERFEVTSEL1)
MSR 0x000003F8 = 0x00000000:0x00000000 (MSR_PKG_C4_RESIDENCY)
MSR 0x000003F9 = 0x00000000:0x00000000 (MSR_PKG_C6C_RESIDENCY)
MSR 0x000003FA = 0x00000000:0x00000000 (MSR_PKG_C6_RESIDENCY)
MSR 0x000004E0 = 0x00000000:0x00000000 (MSR_SMM_FEATURE_CONTROL)
MSR 0x000004E2 = 0x00000000:0x00000000 (MSR_SMM_DELAYED)
MSR 0x000004E3 = 0x00000000:0x00000FFA (MSR_SMM_BLOCKED)
MSR 0x00000606 = 0x00000000:0x000A0E03 (MSR_RAPL_POWER_UNIT)
MSR 0x0000060A = 0x00000000:0x00008842 (MSR_PKGC3_IRTL)
MSR 0x0000060B = 0x00000000:0x00008873 (MSR_PKGC_IRTL1)
MSR 0x0000060C = 0x00000000:0x00008891 (MSR_PKGC_IRTL2)
MSR 0x0000060D = 0x00000000:0x00000000 (MSR_PKG_C2PUP_RESIDENCY)
MSR 0x00000610 = 0x00428212:0x001A81A8 (MSR_PKG_TURBO_POWER_LIMIT)
MSR 0x00000611 = 0x00000000:0x05478696 (MSR_PKG_ENERGY_STATUS)
MSR 0x00000613 = 0x00000000:0x00000000 (MSR_PKG_PERF_STATUS)
MSR 0x00000614 = 0x00000000:0x000001A8 (MSR_PKG_TURBO_POWER_INFO)
MSR 0x00000619 = 0x00000000:0xFA9629F6 (MSR_DRAM_ENERGY_STATUS)
MSR 0x0000061B = 0x00000000:0x00000000 (MSR_DRAM_PERF_STATUS)
MSR 0x00000638 = 0x00000000:0x00000000 (MSR_PPO_TURBO_POWER_LIMIT)
MSR 0x00000639 = 0x00000000:0x42022D5D (MSR_PPO_ENERGY_STATUS)
MSR 0x0000063A = 0x00000000:0x00000000 (MSR_PP0_POLICY)
MSR 0x00000640 = 0x00000000:0x00000000 (MSR_PP1_POWER_LIMIT)
MSR 0x00000641 = 0x00000000:0x00000000 (MSR_PP1_ENERGY_STATUS)
MSR 0x00000642 = 0x00000000:0x00000010 (MSR_PP1_POLICY)
MSR 0x00000648 = 0x00000000:0x0000001C (MSR_CONFIG_TDP_NOMINAL)
MSR 0x00000649 = 0x00000000:0x00000000 (MSR_CONFIG_TDP_LEVEL1)
MSR 0x0000064A = 0x00000000:0x00000000 (MSR_CONFIG_TDP_LEVEL2)
MSR 0x0000064B = 0x00000000:0x80000000 (MSR_CONFIG_TDP_CONTROL)
MSR 0x0000064C = 0x00000000:0x00000000 (MSR_TURBO_ACTIVATION_RATIO)
MSR 0x00000690 = 0x00000000:0x00000000 (MSR_CORE_PERF_LIMIT_REASONS)
MSR 0x000006B0 = 0x00000000:0x00000000 (MSR_GRAPHICS_PERF_LIMIT_REASONS)
MSR 0x000006B1 = 0x00000000:0x0C000000 (MSR_RING_PERF_LIMIT_REASONS)
MSR 0x00000700 = 0x00000000:0x00000000 (MSR_UNC_CBO_0_PERFEVTSEL0)
MSR 0x00000701 = 0x00000000:0x00000000 (MSR_UNC_CBO_0_PERFEVTSEL1)
MSR 0x00000706 = 0x00000000:0x00000000 (MSR_UNC_CBO_0_PERFCTR0)
MSR 0x00000707 = 0x00000000:0x00000000 (MSR_UNC_CBO_0_PERFCTR1)
MSR 0x00000710 = 0x00000000:0x00000000 (MSR_UNC_CBO_1_PERFEVTSEL0)
MSR 0x00000711 = 0x00000000:0x00000000 (MSR_UNC_CBO_1_PERFEVTSEL1)
MSR 0x00000716 = 0x00000000:0x00000000 (MSR_UNC_CBO_1_PERFCTR0)
MSR 0x00000717 = 0x00000000:0x00000000 (MSR_UNC_CBO_1_PERFCTR1)
MSR 0x00000720 = 0x00000000:0x00000000 (MSR_UNC_CBO_2_PERFEVTSEL0)
MSR 0x00000721 = 0x00000000:0x00000000 (MSR_UNC_CBO_2_PERFEVTSEL1)
MSR 0x00000726 = 0x00000000:0x00000000 (MSR_UNC_CBO_2_PERFCTR0)
MSR 0x00000727 = 0x00000000:0x00000000 (MSR_UNC_CBO_2_PERFCTR1)
MSR 0x00000C80 = 0x00000000:0x40000000 (IA32_DEBUG_FEATURE)

====================== UNIQUE MSRs (core 0) ======================
MSR 0x00000000 = 0x00000000:0x000000FF (IA32_P5_MC_ADDR)
MSR 0x00000001 = 0x00000000:0x00000000 (IA32_P5_MC_TYPE)
MSR 0x00000006 = 0x00000000:0x00000040 (IA32_MONITOR_FILTER_LINE_SIZE)
MSR 0x00000010 = 0x00095BE6:0x79E86148 (IA32_TIME_STAMP_COUNTER)
MSR 0x0000001B = 0x00000000:0xFEE00900 (IA32_APIC_BASE)
MSR 0x00000034 = 0x00000000:0x00000058 (MSR_SMI_COUNT)
MSR 0x0000003A = 0x00000000:0x00000005 (IA32_FEATURE_CONTROL)
MSR 0x0000003B = 0x00000000:0x00000000 (IA32_TSC_ADJUST)
MSR 0x0000008B = 0x00000017:0x00000000 (IA32_BIOS_SIGN_ID)
MSR 0x000000C1 = 0x00000000:0x0000ABCD (IA32_PMC0)
MSR 0x000000C2 = 0x00000000:0x00000000 (IA32_PMC1)
MSR 0x000000C3 = 0x00000000:0x00000000 (IA32_PMC2)
MSR 0x000000C4 = 0x00000000:0x00000000 (IA32_PMC3)
MSR 0x000000E2 = 0x00000000:0x1E008403 (MSR_PKG_CST_CONFIG_CONTROL)
MSR 0x000000E4 = 0x00000000:0x00010514 (MSR_PMG_IO_CAPTURE_BASE)
MSR 0x000000E7 = 0x000003A3:0x93F22B7C (IA32_MPERF)
MSR 0x000000E8 = 0x00000391:0x6BAD4F38 (IA32_APERF)
MSR 0x000000FE = 0x00000000:0x00000D0A (IA32_MTRRCAP)
MSR 0x00000174 = 0x00000000:0x00000060 (IA32_SYSENTER_CS)
MSR 0x00000175 = 0x00000000:0xC2E084A0 (IA32_SYSENTER_ESP)
MSR 0x00000176 = 0x00000000:0xC040999C (IA32_SYSENTER_EIP)
MSR 0x00000179 = 0x00000000:0x00000C07 (IA32_MCG_CAP)
MSR 0x0000017A = 0x00000000:0x00000000 (IA32_MCG_STATUS)
MSR 0x00000186 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL0)
MSR 0x00000187 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL1)
MSR 0x00000188 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL2)
MSR 0x00000189 = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL3)
MSR 0x0000018A = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL4)
MSR 0x0000018B = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL5)
MSR 0x0000018C = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL6)
MSR 0x0000018D = 0x00000000:0x00000000 (IA32_PERF_EVNTSEL7)
MSR 0x00000199 = 0x00000000:0x00001C00 (IA32_PERF_CTL)
MSR 0x0000019A = 0x00000000:0x00000000 (IA32_CLOCK_MODULATION)
MSR 0x0000019B = 0x00000000:0x01000013 (IA32_THERM_INTERRUPT)
MSR 0x0000019C = 0x00000000:0x88440000 (IA32_THERM_STATUS)
MSR 0x000001A0 = 0x00000000:0x00850089 (IA32_MISC_ENABLES)
MSR 0x000001A4 = 0x00000000:0x00000000 (IA32_MISC_FEAT_CONTROL)
MSR 0x000001A6 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_0)
MSR 0x000001A7 = 0x00000000:0x00000000 (MSR_OFFCORE_RSP_1)
MSR 0x000001C8 = 0x00000000:0x00000000 (MSR_LBR_SELECT)
MSR 0x000001C9 = 0x00000000:0x00000000 (MSR_LASTBRANCH_TOS)
MSR 0x000001D9 = 0x00000000:0x00000000 (IA32_DEBUGCTL)
MSR 0x000001DD = 0x00000000:0x00000000 (MSR_LER_FROM_LIP)
MSR 0x000001DE = 0x00000000:0x00000000 (MSR_LER_TO_LIP)
MSR 0x000001F2 = 0x00000000:0x7F800006 (IA32_SMRR_PHYSBASE)
MSR 0x000001F3 = 0x00000000:0xFF800800 (IA32_SMRR_PHYSMASK)
MSR 0x00000200 = 0x00000000:0x80000000 (IA32_MTRR_PHYSBASE0)
MSR 0x00000201 = 0x0000007F:0x80000800 (IA32_MTRR_PHYSMASK0)
MSR 0x00000202 = 0x00000000:0x78000000 (IA32_MTRR_PHYSBASE1)
MSR 0x00000203 = 0x0000007F:0xF8000800 (IA32_MTRR_PHYSMASK1)
MSR 0x00000204 = 0x00000000:0x77000000 (IA32_MTRR_PHYSBASE2)
MSR 0x00000205 = 0x0000007F:0xFF000800 (IA32_MTRR_PHYSMASK2)
MSR 0x00000206 = 0x00000000:0x76800000 (IA32_MTRR_PHYSBASE3)
MSR 0x00000207 = 0x0000007F:0xFF800800 (IA32_MTRR_PHYSMASK3)
MSR 0x00000208 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE4)
MSR 0x00000209 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK4)
MSR 0x0000020A = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE5)
MSR 0x0000020B = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK5)
MSR 0x0000020C = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE6)
MSR 0x0000020D = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK6)
MSR 0x0000020E = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE7)
MSR 0x0000020F = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK7)
MSR 0x00000210 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE8)
MSR 0x00000211 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK8)
MSR 0x00000212 = 0x00000000:0x00000000 (IA32_MTRR_PHYSBASE9)
MSR 0x00000213 = 0x00000000:0x00000000 (IA32_MTRR_PHYSMASK9)
MSR 0x00000250 = 0x06060606:0x06060606 (IA32_MTRR_FIX64K_00000)
MSR 0x00000258 = 0x06060606:0x06060606 (IA32_MTRR_FIX16K_80000)
MSR 0x00000259 = 0x00000000:0x00000000 (IA32_MTRR_FIX16K_A0000)
MSR 0x00000268 = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_C0000)
MSR 0x00000269 = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_C8000)
MSR 0x0000026A = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_D0000)
MSR 0x0000026B = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_D8000)
MSR 0x0000026C = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_E0000)
MSR 0x0000026D = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_E8000)
MSR 0x0000026E = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F0000)
MSR 0x0000026F = 0x05050505:0x05050505 (IA32_MTRR_FIX4K_F8000)
MSR 0x00000277 = 0x00070106:0x00070106 (IA32_PAT)
MSR 0x00000280 = 0x00000000:0x40000001 (IA32_MC0_CTL2)
MSR 0x00000281 = 0x00000000:0x40000001 (IA32_MC1_CTL2)
MSR 0x00000282 = 0x00000000:0x40000001 (IA32_MC2_CTL2)
MSR 0x00000283 = 0x00000000:0x40000001 (IA32_MC3_CTL2)
MSR 0x000002FF = 0x00000000:0x00000C06 (IA32_MTRR_DEF_TYPE)
MSR 0x00000309 = 0x00000000:0x00000000 (IA32_FIXED_CTR0)
MSR 0x0000030A = 0x00000000:0x00000000 (IA32_FIXED_CTR1)
MSR 0x0000030B = 0x00000000:0x00000000 (IA32_FIXED_CTR2)
MSR 0x00000345 = 0x00000000:0x000032C4 (IA32_PERF_CAPABILITIES)
MSR 0x0000038D = 0x00000000:0x00000000 (IA32_FIXED_CTR_CTRL)
MSR 0x0000038E = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_STATUS)
MSR 0x0000038F = 0x00000000:0x000000FF (IA32_PERF_GLOBAL_CTRL)
MSR 0x00000390 = 0x00000000:0x00000000 (IA32_PERF_GLOBAL_OVF_CTRL)
MSR 0x000003F1 = 0x00000000:0x00000000 (MSR_PEBS_ENABLE)
MSR 0x000003F6 = 0x00000000:0x0000FFFF (MSR_PEBS_LD_LAT)
MSR 0x000003FC = 0x00000000:0x04FD1380 (MSR_CORE_C4_RESIDENCY)
MSR 0x000003FD = 0x000957A7:0xE39CDE58 (MSR_CORE_C6_RESIDENCY)
MSR 0x000003FD = 0x000957A7:0xE39CDE58 (MSR_CORE_C7_RESIDENCY)
MSR 0x00000400 = 0x00000000:0x000000FF (IA32_MC0_CTL)
MSR 0x00000401 = 0x00000000:0x00000000 (IA32_MC0_STATUS)
MSR 0x00000402 = 0x00000000:0x00000000 (IA32_MC0_ADDR)
MSR 0x00000403 = 0x00000000:0x00000000 (IA32_MC0_MISC)
MSR 0x00000404 = 0x00000000:0x0000000F (IA32_MC1_CTL)
MSR 0x00000405 = 0x00000000:0x00000000 (IA32_MC1_STATUS)
MSR 0x00000406 = 0x00000000:0x00000000 (IA32_MC1_ADDR)
MSR 0x00000407 = 0x00000000:0x00000000 (IA32_MC1_MISC)
MSR 0x00000408 = 0x00000000:0x0000000F (IA32_MC2_CTL)
MSR 0x00000409 = 0x00000000:0x00000000 (IA32_MC2_STATUS)
MSR 0x0000040A = 0x00000000:0x00000000 (IA32_MC2_ADDR)
MSR 0x0000040B = 0x00000000:0x00000000 (IA32_MC2_MISC)
MSR 0x0000040C = 0x00000000:0x0000000F (IA32_MC3_CTL)
MSR 0x0000040D = 0x00000000:0x00000000 (IA32_MC3_STATUS)
MSR 0x0000040E = 0x00000000:0x00000000 (IA32_MC3_ADDR)
MSR 0x0000040F = 0x00000000:0x00000000 (IA32_MC3_MISC)
MSR 0x00000410 = 0x00000000:0x0000003F (IA32_MC4_CTL)
MSR 0x00000411 = 0x00000000:0x00000000 (IA32_MC4_STATUS)
MSR 0x00000480 = 0x00DA0400:0x00000012 (IA32_VMX_BASIC)
MSR 0x00000481 = 0x0000007F:0x00000016 (IA32_VMX_PINBASED_CTLS)
MSR 0x00000482 = 0xFFF9FFFE:0x0401E172 (IA32_VMX_PROCBASED_CTLS)
MSR 0x00000483 = 0x007FFFFF:0x00036DFF (IA32_VMX_EXIT_CTLS)
MSR 0x00000484 = 0x0000FFFF:0x000011FF (IA32_VMX_ENTRY_CTLS)
MSR 0x00000485 = 0x00000000:0x300481E5 (IA32_VMX_MISC)
MSR 0x00000486 = 0x00000000:0x80000021 (IA32_VMX_CR0_FIXED0)
MSR 0x00000487 = 0x00000000:0xFFFFFFFF (IA32_VMX_CR0_FIXED1)
MSR 0x00000488 = 0x00000000:0x00002000 (IA32_VMX_CR4_FIXED0)
MSR 0x00000489 = 0x00000000:0x000727FF (IA32_VMX_CR4_FIXED1)
MSR 0x0000048A = 0x00000000:0x0000002A (IA32_VMX_VMCS_ENUM)
MSR 0x0000048B = 0x00001CFF:0x00000000 (IA32_VMX_PROCBASED_CTLS2)
MSR 0x0000048C = 0x00000F01:0x06334141 (IA32_VMX_EPT_VPID_ENUM)
MSR 0x0000048D = 0x0000007F:0x00000016 (IA32_VMX_TRUE_PINBASED_CTLS)
MSR 0x0000048E = 0xFFF9FFFE:0x04006172 (IA32_VMX_TRUE_PROCBASED_CTLS)
MSR 0x0000048F = 0x007FFFFF:0x00036DFB (IA32_VMX_TRUE_EXIT_CTLS)
MSR 0x00000490 = 0x0000FFFF:0x000011FB (IA32_VMX_TRUE_ENTRY_CTLS)
MSR 0x00000491 = 0x00000000:0x00000000 (IA32_VMX_FMFUNC)
MSR 0x000004C1 = 0x00000000:0x0000ABCD (IA32_A_PMC0)
MSR 0x000004C2 = 0x00000000:0x00000000 (IA32_A_PMC1)
MSR 0x000004C3 = 0x00000000:0x00000000 (IA32_A_PMC2)
MSR 0x000004C4 = 0x00000000:0x00000000 (IA32_A_PMC3)
MSR 0x000004C5 = 0x00000000:0x00000000 (IA32_A_PMC4)
MSR 0x000004C6 = 0x00000000:0x00000000 (IA32_A_PMC5)
MSR 0x000004C7 = 0x00000000:0x00000000 (IA32_A_PMC6)
MSR 0x000004C8 = 0x00000000:0x00000000 (IA32_A_PMC7)
MSR 0x00000600 = 0x00000000:0x00000000 (IA32_DS_AREA)
MSR 0x000006E0 = 0x00000000:0x00000000 (IA32_TSC_DEADLINE)

McCalpinJohn · ‎02-26-2016

These values clearly show that the core fixed-function counters, the core programmable counters, the uncore fixed-function counters, and the uncore programmable counters are all not-enabled, so they will not count and they will not generate interrupts.

The programming of the IA32_PERF_GLOBAL_CTRL MSR (0x38f) shows that the core fixed-function counters are disabled at this level, but that the core programmable counters are enabled. But since none are enabled in the PERFEVT_SEL registers, they should not be doing anything.

NMI's are discussed in section 6.7 of Volume 3 of the Intel Architecture SW Developer's Manual (document 325384). Since it looks like the performance counters can be ruled out, the next step is probably to attempt to determine if the NMI was generated by an external agent asserting the NMI pin on the processor package, or by receiving an NMI message via the APIC system. At this point my experience with interrupts ends -- I hope you can find someone else who can help with the diagnosis.....

PAgra · ‎02-29-2016

Thank you John for your comment.

I will get a closer look at the section you mentionned concerning the NMIs.

Best regards,
Patrick Agrain

Disabling PMU counters NMI generation