Is it possible to monitor cache state from a HARP IP? My goal is to monitor memory address ranges and act, from the IP side, on modifications in such ranges.
Since the FPGA has a cache coherent with its associated Xeon's LLC, and such coherence is done through QPI transactions, I am wondering if its possible to snoop on such messages and act on them.
Thanks in advance!
PS: I failed to find a HARP specific thread. So, If this is not the correct place to discuss HARP related topics, please direct me to them.