Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
1771 Discussions

[HARP] Hardware Accelerator Research Program

Jde_C
Beginner
‎09-10-2018 01:55 PM
925 Views

 Hi,

Is it possible to monitor cache state from a HARP IP? My goal is to monitor memory address ranges and act, from the IP side, on modifications in such ranges.

Since the FPGA has a cache coherent with its associated Xeon's LLC, and such coherence is done through QPI transactions, I am wondering if its possible to snoop on such messages and act on them.

Thanks in advance!

PS: I failed to find a HARP specific thread. So, If this is not the correct place to discuss HARP related topics, please direct me to them.

0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.