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How "disable_all_allocating_flows" bit affects PCIe reads?

nlnnfn__Alex
Novice
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Hello,

 

I wonder how "disable_all_allocating_flows" bit affects PCIe reads.

From the  Hasswell spec xeon-e5-v3-datasheet-vol-2.pdf,  bit 24 (disable_all_allocating_flows) of iiomiscctrl register controls the DDIO . Its functionality described in the spec as follows:


"When this bit is set, IIO will no more issue any new inbound IDI command that can allocate into LLC. Instead, all the writes will use one of the non-allocating commands -PCIWiL/PCIWiLF/PCINSWr/PCINSWrF."

 

All these are PCIe writes. If I understand it right, enabling this bit effectively disables DDIO for PCIe writes and these are written directly to the memory bypassing the LLC, assuming locality of the NIC/CPU/memory. 

I wonder how this bit affects PCIe reads, if at all?

 

Another question:
Correct me if I wrong, DDIO allows DMA reads to be done from the LLC if data is there, if not the data is brought from the memory to the LLC and then DMA read is performed.

Is it possible to make PCIe reads (DMA reads issued from an IO device) to be fetched directly from the memory if data is not in the LLC already, in order to prevent the LLC pollution? 


Thanks

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Alex_Nln
Beginner
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Any ideas?

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A_T_Intel
Employee
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The allocating flows apply to inbound/upstream writes and does not change behavior of inbound/upstream read requests. 

Regarding the read question, there is no way to issue a read and ignore coherency and go directly to DRAM. Checks have to be made to verify that the address being requested isn't modified in another cache. 

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