How to generate the Performance monitoring interrupt after every "N" retired instructions?

[Sanjeev_D_]

I want to configure the performance counter to generate performance monitoring interrupt (PMI) after N retired instructions. My current set up is: msr pmc0 (0xc1) = -1000, set IA32_PERFEVTSEL0 (0x186)= 0x005100C0, IA32_PERF_GLOBAL_CTRL MSR (0x38F) = 1. Here, N=1000 instructions.

However, I found that the interrupt was generated only once. I expect to get PMI interrupt after each N retired instructions. I also clear the overflow after first interrupt (IA32_PERF_GLOBAL_OVF_CTRL(0x390) = 1).

Could you please let me know how can I generate the interrupt after every N instructions. Any help will be highly appreciated. 

Following is my code:

    //set -10000 as a overflow counter    
        xor edx, edx
        mov eax, 0xFFFFD8F0        
        mov ecx, 0xc1
        wrmsr                
    // set up the event 
        xor edx, edx                 
        mov eax, 0x005100C0       
        mov ecx, 0x186                    
        wrmsr
    //IA32_PERF_GLOBAL_CTRL MSR address    0x38F      
        mov edx, 0x00000000                      
        mov eax, 0x00000001  
        mov ecx, 0x38F                      
        wrmsr
        
    
    //Once the interrupt is encountered, we clear the overflow
    //IA32_PERF_GLOBAL_OVF_CTRL MSR
    mov edx, 0x00000000                       
    mov eax, 0x00000001                 
    mov ecx, 0x390                     
    wrmsr     

[Tokponnon__Parfait]

Hello Sanjeev D.

Have you succeeded in solving this problem?
I am having exactly the same problem now, I receive the first interrupt, reset the counter to the initial count, clear the overflow flag but none of the following overflow interrupt are received...
 

[Ilya_Verbin]

Parfait T. wrote:

I am having exactly the same problem now, I receive the first interrupt, reset the counter to the initial count, clear the overflow flag but none of the following overflow interrupt are received...

Didn't you forget to ack the interrupt in APIC PMI LVT?

[Tokponnon__Parfait]

Verbin, Ilya wrote:

Quote:

Didn't you forget to ack the interrupt in APIC PMI LVT?

Hello Verbin,

What do you mean by "ack - acknowledge"? Can you be more explict?

Are you talking about eoi? if so, my answer is yes

[Ilya_Verbin]

Parfait T. wrote:

Quote:

Verbin, Ilya wrote:

Quote:

Didn't you forget to ack the interrupt in APIC PMI LVT?

What do you mean by "ack - acknowledge"? Can you be more explict?

Yes, when performance monitoring interrupt (PMI) happens, it sets bit #16 in APIC PMI LVT, which means that no other PMI can occur until this bit is 1. So you should set it to 0 at the end of the interrupt handler (in other words: to acknowledge it / to unmask it).

Please look at Figure 10-8. Local Vector Table (LVT) in Intel software developer’s manual.

Interrupt mask: (0) enables reception of the interrupt and (1) inhibits reception of the interrupt. When the local APIC handles a performance-monitoring counters interrupt, it automatically sets the mask flag in the LVT performance counter register. This flag is set to 1 on reset. It can be cleared only by software.