Mistake in Intel Developer Manual Volume 3?

[T_C]

Intel Developer Manual, Volume 3 contains this hardware event counter description:

BACLEAR_FORCE_IQ

Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch Prediction Unit. If the conditional branch target is not found in the Target Array and the IQ predicts that the branch is taken, then the IQ will force the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline.

I have read several of the original Intel patents and they had detailed schematic diagrams showing the Branch Address Calculator (BAC) contains the actual static prediction logic.

Could somebody please confirm/explain this? If its not the BAC, why would an instruction queue be doing static prediction?? (I know why the static prediction is done, I mean it seems odd for a queue to perform it, rather than the BAC).

[McCalpinJohn]

I can't comment on practice at Intel, but I am quite certain that my patents at IBM and AMD bear little resemblance to what went into the actual products.

Of course mistakes in the documentation are not uncommon. 

Does the proper identification of the unit making the branch prediction have any impact on code generation or performance tuning?

[T_C]

John D. McCalpin wrote:

I can't comment on practice at Intel, but I am quite certain that my patents at IBM and AMD bear little resemblance to what went into the actual products.

Of course mistakes in the documentation are not uncommon. 

Does the proper identification of the unit making the branch prediction have any impact on code generation or performance tuning?

No not at all, I am just trying to understand exactly how the CPU works.