[PCM] L2/L3 Cache Miss Values Are Alway Zero on Sandy Bridge

[mikeb01]

Hi,

I've ported the PCM Counter code across to Darwin (Mac OS), the msrtest and cpucounterstest programs both run and produce sensible values for instruction and cycle count, however the L2 & L3 cache values are always zero. Are these counters supported on my CPU revision (below) or is more likely that I've introduced a bug in my port?

CPU:

machdep.cpu.brand_string: Intel Core i7-2677M CPU @ 1.80GHz

machdep.cpu.family: 6

machdep.cpu.model: 42

machdep.cpu.extmodel: 2

machdep.cpu.extfamily: 0

machdep.cpu.stepping: 7

Mike.

[Roman_D_Intel]

Hi Mike,

your processor (model 42)is supported in the recent version of Intel PCM.

How do you access model specific registers on Mac OS? Does Mac OS have an "msr" kernelmodule (like in Linux)?

Thanks,
Roman

[mikeb01]

Hi Roman,

Thanks for the prompt reply! It was a bug in my code, I wasn't setting the cpu_model correctly. Fixed and I now see L2/L3 cache misses.

Mac OS doesn't support this out of the box. I've cobbled together a kernel module that allows me to access MSRs and build CPU topology information. I've replicated the functionality of /dev/cpu/*/msr and /proc/cpuinfo.

Mike.

[Roman_D_Intel]

Hi Mike,

great to hear that it works for you.

Roman