PCU event FREQ_TRANS_CYCLES not changing

[SB17]

        Hi all
        Trying to determine how many cycles are spent on the transition from turbo boost frequency to nominal frequency (event FREQ_TRANS_CYCLES http://www.intel.com/content/dam/www/public/us/en/documents/design-guides/xeon-e5-2600-uncore-guide.pdf page 85).
        In turbostat I can see that the frequency is changing, but then I read the value of FREQ_TRANS_CYCLES does not change when frequeny change.
        Is this normal?
        How I can determine the overhead for changing the frequency?

P.S.
CPU - 2680. Set and read FREQ_TRANS_CYCLES event through msr-tool.

Thank for you time

[SB17]

when looking at the number of responses, then one of two
   or my English is absolutely bad
   or it is common knowledge and it is offtopic

[Patrick_F_Intel1]

Hello Black,

Have you tried an event like TOTAL_TRANSITION_CYCLES (on page 86) and gotten non-zero results?

Programming these counters is not trivial.

Pat

[Bernard]

As Pat hinted you can try to read TOTAL_TRANSITION_CYCLES.

Usually it will be very hard to answer why some counter is not performing as expected. I suppose that exact implementation of specific counter is done probably by micro-code. Very simplistic implementation could count for example the number of retired uop(s) and increment  its counter.

[SB17]

Hi all

Sorry for the long answer (rechecked all) and a lot of letters (trying to explain that all was clear)

I tried TOTAL_TRANSITION_CYCLES. It is always 0. However I have all CPU cores always able to C0 (confirmed by reading events POWER_STATE_OCC - 0x80 <Count cores in C0>. It is always = 8). So it seems logical that reading TOTAL_TRANSITION_CYCLES always get 0.
         Except reading via msr-tool I also try profile value of FREQ_TRANS_CYCLES via Intel Performance Counter Monitor utility - Intel PCM 2.6 (https://software.intel.com/en-us/forums/topic/488468). Is always 0.
        I Try to profiling HPL benchmark.

Description of PCU read may be usefull. Bash is some slow for linpack in P0 and it would look bitter in C but currently i have not time for C coding

Setup FREQ_TRANS_CYCLES (Event Code: 0x00 Extra Select Bit: Y):

                                        Extra
                                        select
                                en      bit     reserv  edge_det reset  reserv  occ_sel reserv  ev_sel
                                22      21      20:19   18       17     16      15:14   13:8    7:0
0000000000000000000000000       1       1       00      0        1      0       01      000000  00000000

Setup TOTAL_TRANSITION_CYCLES:
                                        Extra
                                        select
                                en      bit     reserv  edge_det reset  reserv  occ_sel reserv  ev_sel
                                22      21      20:19   18       17     16      15:14   13:8    7:0
0000000000000000000000000       1       1       00      0        1      0       01      000000  00001011



res="0000000000000000000000000       1       1       00      0        1      0       01      000000  00000000"
echo "obase=16; ibase=2; $res"|sed "s/  *//g" | bc
624000

bash script
        # setup
        cpu=0
        CTR0=0x0C30;
        CTR1=0x0C31;
        ./wrmsr -p $cpu $CTR0 0x424000  #       CTR0    CLOCKTICKS
        ./wrmsr -p $cpu $CTR1 0x624000  #       CTR1    TOTAL_TRANSITION_CYCLES
        PCU_MSR_PMON_BOX_CTL=0C24;
        frz=10100
        rst=10002

        # read with 1 sec interval
        for ((;;)) {
                # frize core box
                MSR=$PCU_MSR_PMON_BOX_CTL; ./wrmsr -p $cpu 0x$MSR 0x$frz;

                #read
                MSR=0C36; interval=47:0; CTR0=`./rdmsr -p $cpu 0x$MSR --c-language --bitfield $interval -u`;
                MSR=0C37; interval=47:0; CTR1=`./rdmsr -p $cpu 0x$MSR --c-language --bitfield $interval -u`;

                FREQ_TRANS_CYCLES=`echo "scale=2; $CTR1 / $CTR0"|sed "s/U//g"|sed "s/0x//g"| bc`

                # reset core box
                MSR=$PCU_MSR_PMON_BOX_CTL; ./wrmsr -p $cpu 0x$MSR 0x$rst;

                sleep 1;
        }

[Bernard]

Maybe higher priviledged OSPM process's thread is accessing/modifying those registers when your bash script code is sleeping.You cannot exclude such a possibility.

[Roman_D_Intel]

could you share the ./pcm-power.x 1 -p 5 output here?

Roman

[SB17]

hi all

Thanks for reply

iliyapolak - I also have 0 than get pcm.

Roman Dementiev - Server in my work. I try to get pcm.out tomorrow

[Bernard]

>>>I also have 0 than get pcm.>>>

Did you mean that pcm tool also returned 0?

[SB17]

Sorry, an error somewhere in my code.

I rechecked all and recheck pcm-power.x 1 -p 5.

pcm-power.x get non zerro value.

I have error like at https://software.intel.com/en-us/forums/topic/517903. If command too long it was necessary to use quotes like " "

mea culpa

[Roman_D_Intel]

Hi Black. S,

no problem. I am glad you have located the issue and pcm-power.x works for you.

Best regards,

Roman

[Bernard]

So the 0 value was related to wrong syntax?

[SB17]

1) In bash I have mistake in this

FREQ_TRANS_CYCLES=`echo "scale=2; $CTR1 / $CTR0"|sed "s/U//g"|sed "s/0x//g"| bc`

Correctly is "scale=6". Pеrcent is so tiny.

2) In pcm I write command like pcm-power.x -p 5 `linpack input.dat`

Correctly is pcm-power.x -p 5 "linpack input.dat"

Elementary error, but did not guess