There are no exposed mechanisms for separating the energy consumption at a finer level of granularity than the "power planes" that RAPL supports. (The activity, voltage, and temperature information used as input to the RAPL model might be available at a finer granularity inside the chip, but there is no mechanism to see it.)
I noticed that the Xeon E5-26xx v3 processors in my lab no longer provide a separate RAPL PP0 (core) energy consumption value (the MSR always returns zero), so it is no longer possible to subtract PP0 energy from Package energy to get an approximation to uncore energy. From reading other documentation about the Xeon E5 v3, it seems that the hardware's ability to control the energy consumption is getting more sophisticated, but there is less detailed information available to the user. It is hard to tell if this is a trend or a one-time retreat on supported functionality.
There is no hardware register presumably MSR type which will report single core power consumption.
Search in Google Patents service following query " Power management coordination in multicore processors"