What PMU events exactly does the Ivy bridge processor support?

[Hao_Shen]

Hi,

I have an ivybridge i3770K machine and I need to some some reseach using the PMU. I just need some help:>

I have read the Doc.325394 Chapter 19 Performance-Monitoring Events. I need to find all the events supported by my machine(to do some data mining stuff:>). I use Perf tool in Ubuntu.

Here is what I found:

1.Architectural performance events in Table19-1 are definitely supported(should be supported by all arch)

2.Events in Table 19-5 Performance monitoring events for 3rd generation intel core processors  are definitely supported.

3. For the unconre events, strangely, only the table for Ivy bridge is missing:< So I suppose the events for the sandy bridge in Table 19-10 should be used for my Ivy bridge processor. Is that right?

4. For some reason, I know there is an event called UNC_IMC_RETRY.ANY. So I searched this in the doc and found it in Table 19-14 (0732H) which is for Westmere. However, I tried this event using the Perf tool on my machine, the reading is not zero! At this point , I became confused. This event is not shown to be supported by the Ivy bridge but can be read in reality.

So can somebody give a hint what PMU events excatly does my processor support?Thanks

[Hao_Shen]

Really need some guidance... :)

[McCalpinJohn]

(1) Have you tried programming the events described in Table 19-10 for the Sandy Bridge i3?   You would probably need a Sandy Bridge i3 system for comparisons, since many of these events are sufficiently obscure that it is hard to know what the right answer should be....

(2) Intel has released information on how to read the memory controller counters on the Core i3/5/7 and Xeon E3 processors.  The document clearly says that the information applies to the Sandy Bridge, Ivy Bridge, and Haswell versions.  The direct link is:
http://software.intel.com/en-us/articles/monitoring-integrated-memory-controller-requests-in-the-2nd-3rd-and-4th-generation-intel

If that link did not survive the posting process, a Google search for:
          "monitoring integrated memory" site:intel.com
should locate the document that I am referring to. 

[Hao_Shen]

John D. McCalpin wrote:

(1) Have you tried programming the events described in Table 19-10 for the Sandy Bridge i3?   You would probably need a Sandy Bridge i3 system for comparisons, since many of these events are sufficiently obscure that it is hard to know what the right answer should be....

(2) Intel has released information on how to read the memory controller counters on the Core i3/5/7 and Xeon E3 processors.  The document clearly says that the information applies to the Sandy Bridge, Ivy Bridge, and Haswell versions.  The direct link is:
http://software.intel.com/en-us/articles/monitoring-integrated-memory-co...

If that link did not survive the posting process, a Google search for:
          "monitoring integrated memory" site:intel.com
should locate the document that I am referring to. 

Hi John,

Thanks a lot for your reply.

For the uncore events, I will try by myself which events in the Table 19-10 is useful.

But for your link of the memory events, I still feel a little confused.... From the link you gave, I can only see a table called "Addresses of DRAM counters ". Do you mean I can use the numbers in that table to program the PMU to show specific memory events? I will give it a shot. But do you have any clue why UNC_IMC_RETRY.ANY. is also supported as I mentioned before? This event seems not to be in the table you gave....

Thanks:>

[McCalpinJohn]

The memory controller performance counters are not accessed using the PMU facilties -- sorry for the confusion.  Mostly I was trying to suggest that since these counters are the same across the 2nd, 3rd, and 4th generation Core i3/5/7 processors, there is (maybe?) a better chance that the events in Table 19-10 are the same as well.

[Hao_Shen]

John D. McCalpin wrote:

The memory controller performance counters are not accessed using the PMU facilties -- sorry for the confusion.  Mostly I was trying to suggest that since these counters are the same across the 2nd, 3rd, and 4th generation Core i3/5/7 processors, there is (maybe?) a better chance that the events in Table 19-10 are the same as well.

 I see. Thanks:)

[Hao_Shen]

John D. McCalpin wrote:

The memory controller performance counters are not accessed using the PMU facilties -- sorry for the confusion.  Mostly I was trying to suggest that since these counters are the same across the 2nd, 3rd, and 4th generation Core i3/5/7 processors, there is (maybe?) a better chance that the events in Table 19-10 are the same as well.

Hi John,

Recently I was doing some research on the PMU of my i7 i3770K processor. I am getting more and more confused about the tables shown in SDM...I am just wondering whether you have any clue...

By "cat /proc/cpuinfo", I have found my CPU is faminly 6 model 58. So I think the Table 19.5 Non-Architectural ....i7,i5,i3 Processors should be used (it claims to support CPUID of 06_3AH processors).

However, I tried some values in Table Table 19-11 Non-Architectural Performance Events In the Processor Core for Intel® Core™ i7 Processor and Intel® Xeon® Processor 5500 Series whose support set doesn't include 06_3AH as claimed. Non-zero values are also shown. And the PMU event numbers are not the same in the two tables.

So it looks that Table 19-5 is only a small subset of supported events of my processor...

[Patrick_F_Intel1]

Hello Hao Shen

The i3770k is a client chip (as opposed to a server chip). See http://ark.intel.com/products/65523 (or google 'intel i3770k' and take the ark.intel.com link).

You should use the ivybridge core events in jun 2013 SDM vol 3 table 19-5.

The uncore architecture changed from Westmere to Sandybridge. Ivybridge uncore architecture is pretty similar to Sandybridge. You can use the events in table 19-10 for the uncore events.

But, I would probably install Intel VTune on your system, and see what events VTune says are available. VTune takes into account all the chip specific programming and events and will show the event list. I don't really know exactly HOW it shows you the events (they keep changing the GUI) but I'm 99.999% sure there is some way to show the events available.

Pat