Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
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What happens in DSB/LSD when an instruction is invalidated using CLFLUSH?


I have a small loop that fit the rules required to use LSD mechanism. The most relevant rule, in this case, is that all the micro-ops are resident in DSB. From the Optimization Manual, it is known that LSD fetches instructions from DSB while it works. It known that LSD ends when a misprediction takes place: "The loop streams from the micro-op queue, with no more fetching, decoding, or reading micro-ops from any of the caches, until a branch misprediction inevitably ends it."

It is also known that DSB is a sort of "L0 cache": it is virtually included in L1 Icache. The Optimization Manual says:"Instruction cache evictions must also be evicted from the Decoded ICache, which evicts only the necessary lines".

The question is the following:

What happens when i run the described loop in a process and i evict one of its intruction from all the caches using CLFLUSH from another process? It's not clear if the micro-ops associated to the instruction are evicted from the DSB and, so the LSD should stop.

My idea is that the eviction of micro-ops in DSB does not take place and the DSB continues to work.

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