Xeon E5-2600 uncore PCU event confusion

[McCalpinJohn]

The Intel Xeon Processor E5-2600 Product Family Uncore Performance Monitoring guide (document 327043-001), section 2.6, describes the performance monitoring capability of the Power Control Unit of the uncore.  At least it tries to describe it...

The first problem is that the entries in Table 2-77 refer to "Voltage/Frequency Band Events".  This is mildly confusing for two reasons: (1) the specification of values appears to be for frequency only, and not for voltage; and (2) there is no discussion of how these frequency values are interpreted as "bands".  Example Case 6 defines the Band 0 value as 0x14 (decimal 20), uses event 0x0B to count cycles in the "Band 0" frequency range, and claims that this will count all cycles with uncore frequency less than 2.0 GHz.  This implies that "Band 0" consists of the frequencies strictly *below* the value in the PCU_MSR_PMON_BOX_FILTER field.   Is this correct?    More importantly, are the other bands inclusive or exclusive?  I.e., if I programmed 0x18 (decimal 24) in the PCU_MSR_PMON_BOX_FILTER:filt15_8 field ("Band 1") would the counts in "Band 1" include the values below the "Band 0" limit of 2.0 GHz, or would it only include the values at or above the "Band 0" limit of 2.0 GHz and strictly below the "Band 1" limit of 2.4 GHz?

The second problem is that the examples in Table 2-80 use different nomenclature than the descriptions of the bit fields of the control registers in Table 2-75.   Most of the names are similar, but there is no reason for them not to be exactly the same names!   Table 2-80 also includes a reference to "UseOccupancy", which does not map to any of the named bit fields from Table 2-75.  By the process of elimination it appears to refer to bit 7 of PCU_MSR_PMON_CTL{3-0}:ev_sel, but this is just an educated guess.  Did I get it right?  Do I get a prize?    If I am correct, then the examples in Table 2-80 are not really defining the PCU_MSR_PMON_CTL:ev_sel bits 7:0, but are actually only defining bits 6:0, with the "UseOccupancy" field defining bit 7.  Is this right?

The third problem is that Table 2-81 listing all the event select fields includes a column labelled "Extra Select Bit".  There is no reference to "Extra Select Bit" anywhere in the document except in tables where it is listed as "0" or "1".   Where is it?  What is it?   The only thing that I can guess is that it might be the logical AND of the filter criteria in the PCU_MSR_PMON_BOX_FILTER register, but that is just a wild guess.  Any help here?

Puzzled, but hopeful...

john

[Roman_D_Intel]

John, Thanks for the feedback. I will forward your findings to the documentation writers. The FREQ_BANDX_CYCLES event description in the section "PCU Box Performance Monitoring Event List" contains information on how the band counting works: "counts the number of cycles that the uncore was running at a frequency greater than or equal to the frequency that is configured in the filter". "Intel Performance Counter Monitor" has a utility called pcm-power.x that you can look into to see how the freq band events are programmed and used. Roman

[Roman_D_Intel]

PCU_MSR_PMON_CTL table definition on page 75 has a note for the ev_sel field: "Bit 7 denotes whether the event requires the use of an occupancy subcounter". You are correct: the UseOccupancy bit mentioned in the examples is bit 7. You can see a usage example in the pcm-power utility included into Intel Performance Counter Monitor.
The extra "Extra Select Bit" is bit 21 of PCU_MSR_PMON_CTL. This bit description will be included in the next revision of the document (not there due to a mistake).
Roman

[McCalpinJohn]

Thanks! This is very helpful... For most counters I can build test cases and compare results to expected behavior, but that is a lot harder for these power control functions. It looks like I gave up before I got all the way down to the detailed event descriptions for FREQ_BAND?_CYCLES. I also missed the setting of the "inversion" bit in Case 6. Now the frequency band filters and events make sense.