(1) In the document "Intel Xeon Procesor E5-2600 Product Family Uncore Performance Monitoring Guide", document 327043-001, March 2012, section 2.7 on QPI Link Layer performance monitoring incorrectly describes the "QPI_RATE_STATUS" register.
Table 2-84 lists the event as having address "0xD4", and section 2.7.3.4 describes this as being an MSR. However, Table 1-3 describes this as being in PCI configuration space at Devices 8/9, Function 0, offset 0xD4.
MSR 0xD4 is not readable on my 2-socket Xeon E5-2680 system, while Bus 3F, Device 8, Function 0, Offset D4 decodes (according to Table 2-93) to a value of 8.0 GT/s, which is the expected value on this system. I noticed that the corresponding location in Function 9 is zero, which I interpret as meaning that the two links are "slaved" to the same frequency, with the frequency only specified in the Link 0 configuration space area.
(2) In Table 2-84 the entries for PKT_MASK and PKT_MATCH are inconsistent. It appears that the fourth entry (Q_Py_PCI_PMON_PKT_MATCH0) should have its "Description" field changed from "Mask 0" to "Match 0".
