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gokussj9
Beginner
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Xeon E5 MSR_PP1_ENERGY_STATUS read/write Error

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http://web.eece.maine.edu/~vweaver/projects/rapl/rapl-read.c

 

I am using the above utility to determine the power consumption of Xeon E5 chip. When I execute the above code on my machine the output is

 


Found Haswell CPU
Checking core #0
Power units = 0.125W
Energy units = 0.00006104J
Time units = 0.00097656s

Package thermal spec: 145.000W
Package minimum power: 69.000W
Package maximum power: 290.000W
Package maximum time window: 0.045898s
Package power limits are unlocked
Package power limit #1: 145.000W for 0.009766s (enabled, clamped)
Package power limit #2: 174.000W for 0.002930s (enabled, clamped)

Package energy before: 238164.254272J
PowerPlane0 (core) for core 0 energy before: 0.000000J
rdmsr:pread: Input/output error

 

 

I determined that the "rdmsr:pread: Input/output error" occurs when trying to read the MSR_PP1_ENERGY_STATUS (0x641). Can anybody tell me why precisely I am getting this error. Am I using a wrong value of the MSR. BTW, this code works just fine on my i5-4430 machine.

 

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1 Solution
Patrick_F_Intel1
Employee
207 Views

Hello gokussj99,

The Xeon chips don't have the integrated graphics and MSR 0x641 is not defined.

You'll notice that the PP0 register is defined but always returns 0. The Haswell Xeon e5 has the RAPL package power. And the DRAM power is defined (and not zero) for the HSW Xeon E5 for which I have data.

Trying to read the SDM vol 3 chapter 35 and figure out which MSrs are on which chips can be challenging. I'm trying to make a script which details which MSRs are supported by which chips or, given a chip and or cpu model number, list all the MSRs for that chip.

Sorry,

Pat

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8 Replies
Patrick_F_Intel1
Employee
208 Views

Hello gokussj99,

The Xeon chips don't have the integrated graphics and MSR 0x641 is not defined.

You'll notice that the PP0 register is defined but always returns 0. The Haswell Xeon e5 has the RAPL package power. And the DRAM power is defined (and not zero) for the HSW Xeon E5 for which I have data.

Trying to read the SDM vol 3 chapter 35 and figure out which MSrs are on which chips can be challenging. I'm trying to make a script which details which MSRs are supported by which chips or, given a chip and or cpu model number, list all the MSRs for that chip.

Sorry,

Pat

View solution in original post

gokussj9
Beginner
207 Views

Hi Patrick,

 

Thanks a lot for your reply. Actually, our group is trying to execute some applications across ARM 64 bit and Xeons and examine the power-performance trade off. I am able to get the package and DRAM energy consumption from the above mentioned routine. 

 

Can you please explain to me what exactly does Package, PP0, PP1 and DRAM power consumptions mean in the context of RAPL measurements.

 

Package=PP0+PP1+DRAM

PP1=PP0+Uncore

PP0=Power consumption of all the cores of a processor.

DRAM= Power consumed by DRAM modules.

Is the above understanding correct? Also Below you can see the output of the RAPL routine. It provides 53.261230J as the energy consumption in 1 second when no application was executing on the processor. Does that mean the processor static power is 53.261230 watts?

Found Haswell CPU
Checking core #0
Reading 0x606
Power units = 0.125W
Energy units = 0.00006104J
Time units = 0.00097656s

Reading 0x614
Package thermal spec: 145.000W
Package minimum power: 69.000W
Package maximum power: 290.000W
Package maximum time window: 0.045898s
Reading 0x610
Package power limits are unlocked
Package power limit #1: 145.000W for 0.009766s (enabled, clamped)
Package power limit #2: 174.000W for 0.002930s (enabled, clamped)

Reading 0x611
Package energy before: 76295.573364J
Reading 0x619
DRAM energy before: 25887.745239J

Sleeping 1 second

Reading 0x611
Package energy after: 76348.834595  (53.261230J consumed)
Reading 0x639
PowerPlane0 (core) for core 0 energy after: 0.000000  (-0.000000J consumed)
Reading 0x619
DRAM energy after: 25892.461609  (4.716370J consumed)

 

Patrick_F_Intel1
Employee
207 Views

So...

package = PP0 + PP1 + uncore.

PP1 = power used by cores

PP1 = power used by integrated graphics

DRAM = power used by dram

Yes, Power in watts over an interval = 'Joules used during interval' / 'interval in seconds' ... so  assuming Mr Weaver's program is calculating everything correctly, it is saying you used ~53 watts during the interval. The "Package minimum power = 69 watts" so the 53 watts compares reasonably. The question "Does that mean the processor static power is 53.261230 watts?" is harder... and unclear. If you mean, is 53 watts the lowest amount of power the processor can use? I just don't know. I'd be curious to see what %time is spent in which package Cstates. If the package is ~99% in C7 cstate then I'd say that is probably the lower limit of the package... which we sometimes call 'the idle power'.

Pat

Patrick_F_Intel1
Employee
207 Views

I meant to say:

PP0 = power used by cores

gokussj9
Beginner
207 Views

Ok. So I have two Xeon E5 2699 on motherboard.  Does each core provides the power consumed in the socket it is situated in? In case I want to measure power across both 2699's, I will have individually measure power on cores in that socket and add up those values to get the total power consumption?

Patrick_F_Intel1
Employee
207 Views

Yes, you have to measure the RAPL package power on each socket and sum them together to get the total power used by the packages. The energy used by the cores on each socket will be reflected in the package power of their socket. When you say "I will have to measure power on cores in that socket"... this is confusing to me. On the Xeon E5-2699 v3 you can only get RAPL package power and RAPL DRAM power. The RAPL PP0 (cores) power is always zero. And the RAPL PP1 register is not defined.

gokussj9
Beginner
207 Views

Sorry for the confusion. Its just that there are so many terms and their meaning isn't very clear at first. So package power is basically the socket power consumption including the integrated graphics. Right? If it does, that means if I were to measure package power from any core of a quad core socket, I would be getting identical numbers?

Patrick_F_Intel1
Employee
207 Views

All the RAPL registers have 'package' scope meaning that if you read the MSR from any core on the package you will get the same value.

Package power (on Xeon E5-2699 V3) = "cores power" + "rest of the package power". There isn't any integrated graphics on this chip.

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