Software Tuning, Performance Optimization & Platform Monitoring
Discussion regarding monitoring and software tuning methodologies, Performance Monitoring Unit (PMU) of Intel microprocessors, and platform updating.
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intel memory latency checker idle/c2c latency mechanics?


The paragraph in question reads:

9.2.4 Measuring cache hit latency
mlc --idle_latency –b3000 –c0 –t3
This command measures the L3 cache hit latency. Since the buffer allocated is only 3MB in size, repeated accesses to the same buffer ensures that all the lines in this buffer will reside in L3 cache (assuming the L3 size is more than 3MB). So, the latency measured would represent the cache hit latency.

My question is, if I add a -C option to specify a window, for example, 128KB,what does the latency number mean? Does this number mean the total time it took to gather all 128KB of data from all L3 slices, or does it mean the response time when the core receives the first slice of data from L3?

The same question goes for the c2c latency tests, does the reported latency reflects the complete data package(for example, 128KB) transaction time, or it stops counting when the other core start to receive data?

Thank you.

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