- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi,
We notice that VTune Amplifier's Memory Access analysis can attribute performance events to memory objects (data structures) based on performance counters (https://software.intel.com/en-us/memory-access-analysis-lin).
We are wondering if there are any APIs that allow programmers to do the similar thing in a program.
Thank you.
Link Copied
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
VTune uses binary instrumentation of memory allocations/deallocations (based on PIN) to get memory object mapping to data addresses over time. Extracting data linear address from PEBS buffers of precise events allows to correlate them with the memory objects.
May I ask what kind of a use case do you have to get an API on this? Writing your own tool to generate performance reports or get data inside the application to make it more dynamic?
Thanks & Regards, Dmitry
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
dmitry-prohorov (Intel) wrote:
Hello,
VTune uses binary instrumentation of memory allocations/deallocations (based on PIN) to get memory object mapping to data addresses over time. Extracting data linear address from PEBS buffers of precise events allows to correlate them with the memory objects.
May I ask what kind of a use case do you have to get an API on this? Writing your own tool to generate performance reports or get data inside the application to make it more dynamic?
Thanks & Regards, Dmitry
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The data linear address comes together with the event. It is a field in the PEBS (Precise Event Based Sampling) record available for some events. So whenever cache miss counter overflowed and you got PMI you can read data address from PEBS which caused that last cache miss which resulted in the overflow.
Detailed information can be found in the Software Developer's Manual, volume 3, chapter 18.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Dmitry Ryabtsev (Intel) wrote:
The data linear address comes together with the event. It is a field in the PEBS (Precise Event Based Sampling) record available for some events. So whenever cache miss counter overflowed and you got PMI you can read data address from PEBS which caused that last cache miss which resulted in the overflow.
Detailed information can be found in the Software Developer's Manual, volume 3, chapter 18.
Thanks Dmitry, it's really helpful.
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page