According to https://www.agner.org/optimize/instruction_tables.pdf (page 193), the "push" instruction on an Ivy Bridge processor has a latency of three cycles. Page 195 reports that the "jmp" instruction has a maximum throughput of one instruction every 2 cycles on Ivy Bridge. From those values an IPC of 1.00 seems reasonable enough.
For test cases like this -- single thread, 10-second runtime -- "perf stat" usually manages to report reasonable counter values.
Estimating the "expected" IPC can be tricky, especially when there are multiple uops in an instruction or multiple instructions that fuse into a single uop. Agner's Instruction Tables provide good information about these cases. Agner's Microarchitecture document is very helpful for understanding the historical progression of the implementations https://www.agner.org/optimize/microarchitecture.pdf