Arria II with single DDR3 SODIMM

[Altera_Forum]

Hello, 

 I am trying to use an Arria II with a single DDR3 SODIMM and was wondering if I can avoid parallel termination and use a simpler termination scheme. I can place the SODIMM as close to the FPGA as I need to. I read the Altera app notes on DDR3 but their examples either use two SODIMMs or talk about features in Stratix IV that are not available in Arria II.  Thank you

[Altera_Forum]

What termination are you referring to? I believe Arria II does have on-chip termination for DQ and DQS lines. 

 Jake

[Altera_Forum]

Jake, 

 You are correct; Arria II does have termination for DQ and DQS and I should be able to use a point-to-point termination as illustrated on page 10 of AN520. I believe most or all of the other signals are terminated on the DIMM and a point to point scheme should work fine.  My confusion started as I read through AN520 in the Arria II section in which they suggest using the DDR2 guidelines. So, I looked at what they did in the Arria II Dev board, and they did not use a point to point topology for either the DDR2 DIMM or the DDR3 chip. Was that by choice or was there a limitation that caused them to do so?  I will do pre/post layout simulation eventually, but wanted to start in the right direction.

[Altera_Forum]

I should have paid more attention. 

 Arria II GX does not support DDR3 DIMMs.  The reason for this is that DDR3 DIMMs are laid out such that the address and command signals daisy chain from component to component on the DIMM. This layout requires that the interface controller (FPGA in this case) support write and read leveling. Leveling basically means that the DQ/DQS groups are written or captured in sequential order to ensure proper timing with the address/command signals as they arrive at each component on the DIMM.  Prior to DDR3, the components were laid out on the DIMM using a standard T topology.  So, you can't drive a DDR3 DIMM with Arria II GX. You can however, layout standard components on your PCB similar to a DDR2 DIMM topology.  Jake

[Altera_Forum]

As an additional point: It seems like AN520 has been silently withdrawn. It's no longer on the Altera website. So I wonder, if it's wrong in any regard? Also no other ANs related to DDR3 can be found.

[Altera_Forum]

Jake, thank you for the critical feedback - you saved me a lot of time. Too bad the Arria II doc is not clear about this. I was trying to save board space by using a DIMM, but I will probably follow your suggestion and put the chips on the main board. Too bad read/write leveling is only available in the Stratix family... 

 FvM, I thought I had just download AN520 in the last few days, but you are right; it's gone now. I hope it will be replaced with a more up to date version.  Thanks for all the help!