Vertical and Horizontal Sync Signal

[Altera_Forum]

does anyone know how to write the code in VHDL by using Quartus 2 to control or generate these two signal?? 

i need to use it to generate color on the CRT monitor screen..  how does the code look like actually? 2 counter?? or array??  URGENT, some one pls help me..... time is running out here!!

[Altera_Forum]

Moin, 

 I've not done anything like this yet, but i'd say, that you'd need conters anyway for addressing the Memory, where your pixeldata is located. Generating from this counter(s) the H/V Sync signals should be mor or less just a by-product. The counters do have to count for more than just the desired number of displayed pixel to get the time for blanking and the sync signal itself. Example: Timing of one line of PAL video:  One line including flyback takes 64usec and might e.g. consist of 864 cycles with 1/13.5MHz each. In this line there are 720 pixel read out, blanking takes the rest (that's 864-720=144 cycles). Within the blanking period, the H-Sync must be generated with a length of 64 cycles... In this case, the H-sync pulse ususally is low during the sync, so it's more a /H-Sync than a H-Sync. What kind of Video/Sync signal do you want to generate? Interlaced/Non-Interlaced? Which resolution? Which frequencies? Composite oder seperate Sync...?  Cheers WK

[Altera_Forum]

Check out vga_ram.vhd in this zip file: 

 http://www.divshare.com/download/1238611-bbc  I didn't write the code, but I know it is a VGA controller that uses RAM on a Spartan-3 board. vga_ram.vhd appears to contain the code that generates the VGA vsync and hsync timing.  Basically, you use the pixel clock to increment a horizontal counter, and use the horizontal counter to increment a vertical counter. As long as the two counts are within range (say 0 < h_count < 640 and 0 < v_count < 480) then provide valid data.

[Altera_Forum]

--- Quote Start ---  does anyone know how to write the code in VHDL by using Quartus 2 to control or generate these two signal?? i need to use it to generate color on the CRT monitor screen..  how does the code look like actually? 2 counter?? or array??  URGENT, some one pls help me..... time is running out here!!  --- Quote End ---   I think you have to be more specific of what you are trying to do. What kind of interface is it? VGA? Analog component (RGB/YUV)? Analog composite (NTSC/PAL)? DVI? Scart-RGB? S-video? HDMI? What resolution? Frame rate? Progressive or interlace scan? What's your interfacing circuits on your board? DAC?  Here's a web page with some useful info of the sync signals for some different VGA resolutions. http://web.mit.edu/6.111/www/s2004/newkit/vga.shtml (http://web.mit.edu/6.111/www/s2004/newkit/vga.shtml)  My suggestion is that you use one line counter and one pixel counter and decode them for setting/resetting H- and V-sync flag. Set the V and H sync signal output to the sync level when the corresponding flag is set. If using sync in the video signal (on green) you should xor the flags before setting the sync level. Remember to set the video to blanking level when the counters are not in active video area. Blanking is usually at level 16 when using an 8 bit DAC.

[Altera_Forum]

--- Quote Start ---  Check out vga_ram.vhd in this zip file:  http://www.divshare.com/download/1238611-bbc  I didn't write the code, but I know it is a VGA controller that uses RAM on a Spartan-3 board. vga_ram.vhd appears to contain the code that generates the VGA vsync and hsync timing.  Basically, you use the pixel clock to increment a horizontal counter, and use the horizontal counter to increment a vertical counter. As long as the two counts are within range (say 0 < h_count < 640 and 0 < v_count < 480) then provide valid data.  --- Quote End ---    Could you re-upload the file ? It has expired.  Many thanks.

[Altera_Forum]

Ok, now it's at: 

http://www.divshare.com/download/1385521-c9d

[Altera_Forum]

rjackal, can you please re upload this file.. pretty please..

[Altera_Forum]

Sorry, that was several years ago and I can't find the file anymore.