Tag: "FPGA"

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A question regarding running the PAM-4 example files for the Stratix 10 TX FPGA by roy970509 Novice in Intel® Quartus® Prime Software 04-22-2024 0 7	0	7
ARRIA10 GX partial reconfiguration by bkanal Novice in FPGA, SoC, And CPLD Boards And Kits 04-21-2024 0 3	0	3
ALTPLL Megawizard crashes by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 04-05-2024 0 21	0	21
help with signal tap - copy and group by CosmoKramer Employee in Programmable Devices 04-04-2024 0 3	0	3
mipi max speed by kikoss Novice in FPGA Intellectual Property 04-01-2024 0 3	0	3
DE10-Lite LED segment seems broken by asp211 Beginner in Programmable Devices 03-28-2024 0 6	0	6
Have you checked out awesome-oneapi? by MaxTerry Employee in Tools 03-26-2024 1 2	1	2
Nios2 Helloworld project Memory Overflow by anonimcs New Contributor I in Nios® V/II Embedded Design Suite (EDS) 03-18-2024 0 12	0	12
Quartus Fitter Crashing by mikeyl Novice in Intel® Quartus® Prime Software 03-14-2024 0 30	0	30
Intel FPGA AI Suite: Glibc v2.32-2.35 not found by ManuDwivedi Novice in Intel® FPGA Software Installation & Licensing 03-05-2024 0 5	0	5
FPGA Download Cable (1) CE Certificate / Declaration of Conformity by Gertschi Beginner in Programmable Devices 03-04-2024 0 6	0	6
eSPI Agent Core by WFitt Novice in Programmable Devices 02-22-2024 0 8	0	8
Max 10 Jtag secure mode issues for lock/unlock jtag by crazy_buddy1164 Beginner in FPGA Intellectual Property 02-06-2024 0 10	0	10
How do I boot HPS of Cyclone V SoC on AMP by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 01-28-2024 0 7	0	7
Boot two cores in cyclone V with two different programs or OS? by Altera_Forum Honored Contributor II in Nios® V/II Embedded Design Suite (EDS) 01-28-2024 0 10	0	10
Quartus crashes when saving a file in project (can't save any files) - PLEASE HELP!! by Lily14 Beginner in Intel® Quartus® Prime Software 01-28-2024 0 4	0	4
omz_converter not working by sarathfv Beginner in Intel® Distribution of OpenVINO™ Toolkit 01-23-2024 1 4	1	4
Can I synthesize HDL, obtained as a result of DPC++ compilation, in Vivado for Xilinx FPGA? by Vladislav-Butko-bvo Novice in Programmable Devices 01-21-2024 0 6	0	6
FPGA AI SUITE by sarathfv Beginner in Intel® Distribution of OpenVINO™ Toolkit 01-18-2024 0 2	0	2
Selection a FPGA/CPLD by hexxx Beginner in Programmable Devices 01-08-2024 0 3	0	3
MTBF by annoyedhuman6969 Beginner in FPGA, SoC, And CPLD Boards And Kits 01-01-2024 0 3	0	3
JTAG connection Issues with Intel FPGA Development Environment by roy970509 Novice in Intel® Quartus® Prime Software 12-29-2023 0 13	0	13
Compile for FPGA hardware failed by Syhuang Novice in Intel® DevCloud 12-11-2023 0 5	0	5
Agilex 7: Not able to access the FPGA fabric from HPS through light weight AXI bus by spectralsensors Novice in FPGA, SoC, And CPLD Boards And Kits 12-07-2023 0 8	0	8
Power up the device(CYCLONE 5) in temperature under zero by sn681 Novice in FPGA, SoC, And CPLD Boards And Kits 12-04-2023 0 23	0	23