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	Software driver for Compact PCI using PCI compiler megacore by dinhlx Novice in FPGA Intellectual Property 06-28-2021 0 3	0	3
	Avalon Dual-Master Bus with constant waitrequest on connection point by MKlee2 New Contributor I in FPGA Intellectual Property 07-16-2020 0 3	0	3
	Intel triple speed Ethernet ip in combination with stratix 10 native phy (H-Tile) usable? by MKlee2 New Contributor I in FPGA Intellectual Property 06-05-2020 0 2	0	2
	Intel DisplayPort IP - DPCD Register Access by DZuck1 Novice in FPGA Intellectual Property 06-01-2020 0 13	0	13
	IP Cores required for generating programming file for PAC with Arria 10 GX FPGA by RBash Novice in FPGA Intellectual Property 03-21-2020 0 3	0	3
	DDR3 UniPHY master/slave by EBoln New Contributor I in FPGA Intellectual Property 03-06-2020 0 3	0	3
	not able to generate sdo for arria 10 soc for post-synthesis timing simulation by VenkateshSathar New Contributor I in FPGA Intellectual Property 01-20-2020 0 8	0	8
	Intel DisplayPort Example Project Fails to Generate Simulation (Quartus Pro v19.1/v19.2) by DZuck1 Novice in FPGA Intellectual Property 12-23-2019 0 9	0	9
	Stratix 10 - 10G LL MAC Ignoring Set_False_Path commands in auto-generated SDC file by DZuck1 Novice in FPGA Intellectual Property 12-18-2019 0 10	0	10
	Avalon Master/ Slave Template Third Party Questasim Simulation by CBOLL2 Beginner in FPGA Intellectual Property 11-15-2019 0 2	0	2
	Does Intel HLS Compiler combine or split variables? by mnazemi Beginner in FPGA Intellectual Property 10-03-2019 0 4	0	4
	Is it possible to skip the generation of cosimulation support in the Intel HLS Compiler? by mnazemi Beginner in FPGA Intellectual Property 09-20-2019 0 2	0	2
	How to call an IP designed in Verilog in Intel HLS compiler? by mnazemi Beginner in FPGA Intellectual Property 09-19-2019 0 1	0	1
	How to convert combinational blocks to sequential blocks automatically? by mnazemi Beginner in FPGA Intellectual Property 09-13-2019 0 3	0	3
	How can i use Quad SPI to talk with Flash memory ? by senjd Novice in FPGA Intellectual Property 09-05-2019 0 9	0	9
	Model-Sim tries to compile header files not included in my project and fails. Model-Sim also fails to instantiate FIFOs and potentially other IPs because it looks it the work_rtl library instead of the altera_mf library by SAbde7 Beginner in FPGA Intellectual Property 09-04-2019 0 1	0	1
	No fpga detection by doing lspci by ADua0 Beginner in FPGA Intellectual Property 07-22-2019 0 7	0	7
	How do I connect Verilog modules I created with ARM processor (HPS) of Cyclone V SOC ? by NShin5 Beginner in FPGA Intellectual Property 06-28-2019 0 1	0	1
	Is there any reason why the LPM ip core (once included in quartus 15.1) is not available in Quartus 18.1? by VBart Beginner in FPGA Intellectual Property 06-03-2019 0 3	0	3
	Device creation test. Do not flag. by JCheah Novice in FPGA Intellectual Property 03-21-2019 0 0	0	0
	Using Intel IPs into our custom IP design by ASuba Novice in FPGA Intellectual Property 01-25-2019 0 6	0	6
	After some transactions waitrequest/ready signal deasserted from DDR3 uniphy memory controller for arria v gx? by senjd Novice in FPGA Intellectual Property 01-24-2019 0 8	0	8
	WHAT IS THE DIFFERENCE BETWEEN MSGDMA AND SGDMA? by KSwam3 Beginner in FPGA Intellectual Property 01-18-2019 0 1	0	1
	What is the best way for a NIOS II to communicate with the DDR3 SDRAM on the Cyclone 10 GX dev kit? by MSimp5 Beginner in FPGA Intellectual Property 01-09-2019 0 6	0	6
	Simulating SCFIFO in modelsim by AKhan15 Beginner in FPGA Intellectual Property 11-22-2018 0 4	0	4