How to call an IP designed in Verilog in Intel HLS compiler?

[mnazemi]

Is it possible to design and optimize an IP in Verilog and create a function for it that can be called from HLS?

A simple example of such scenario would be as follows:

1. Design and optimize an FIR filter in Verilog.
2. Create a function for the design in HLS.
3. Write a nested `for` loop in HLS that calls the function associated with the filter.

[MEIYAN_L_Intel]

Hi,

Since you created the design in HDL for a FIR, you can directly use it. You will eventually get HDL after HLS compilation.

Thanks.