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Ayam
Beginner
103 Views

Appropritate PMU for intel atom avoton

I am looking for the comparison of two architectures, intel xeon (sandy bridge) and intel atom (avoton).

For the analysis, the selected PMU from the xeon architecture are listed below. 

IDQ_UOPS_NOT_DELIVERED.CORE

UOPS_ISSUED.ANY

UOPS_RETIRED.RETIRED_SLOTS

INT_MISC.RECOVERY_CYCLES

however, I could not find the similar parameters in Intel Atom.  I was wondering if somebody can direct me how to find the proper PMU for intel atom (avoton), that would be great.

Regards, 

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2 Replies
Peter_W_Intel
Employee
103 Views

It seemed that supported events on Atom are less than Xeon processor, only commonly events are ready...such as  Cache Miss, Branch Misprediction, UOPS_Retired, OFFCORE_*, etc.

As your request, I found that UOPS_RETIRED.ALL event can be used, but IDQ_UOPS_ events are only available since SandyBridge or later.

 

McCalpinJohn
Black Belt
103 Views

It is sometimes tricky to figure out how to translate code names for the Atom processors, but it looks like the performance counters for the Atom processors in "Avoton" products are "Silvermont" cores.   The performance counters are described in Sections 18.5 and 18.6 of the "Intel64 and IA-32 Architectures Software Developer's Manual: Volume 3: System Programming Guide", document 325384, revision 055, June 2015.

The performance counter events supported by the Atom core are listed in Section 19.12 of the same manual.

Figuring out how performance counter events relate between the two microarchitectures is left as an exercise for the reader (though a lot can be learned from reviewing the use of the events by the Intel VTune tool).

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