Adding an Avalon FIFO IP with PCIeDMA Transfer Example design (Provided in CD) for Arria 10 GX FPGA

[travisa]

Hi,

I am trying to stream in data from an external source (through QSFP+)  to the  DDR4 memory and then do a DMA transfer the data to a Computer through PCIe.

For that I would like to use a FIFO to push data  (that comes from QSFP+) into the DDR4 elements.

My plan is to integrate the Avalon FIFO Memory Intel FPGA IP with the  PCIe DMA transfer example design for Windows (Provided in DE5a-Net CD/Demonstrations/PCIe_DDR4/) mention in the Chapter-7 (section 7.6 from page number 130) of the attached manual (DE5a-Net Arria 10 FPGA) DE5a-Net_User_Manual.pdf. 

Any suggestion or documentation for an additional IP with an example design is most welcome.

PS: I am working in DE5a-Net-DDR4 Arria 10 GX (10 AX115N2F45E1SG) and use Quartus Prime Pro version 18.1

[AdzimZM_Intel]

Hi travisa,

There is another thread that has been created with similar description on https://community.intel.com/t5/FPGA-Intellectual-Property/Integrating-a-Avalon-FIFO-IP-to-the-PCIe-DMA-transfer-example/m-p/1427485#M26591

Please post your related question in previous thread. This thread will be transitioned to community support.

Thank you.