I am trying to stream in data from an external source (through QSFP+) to the DDR4 memory and then do a DMA transfer the data to a Computer through PCIe.
For that I would like to use a FIFO to push data (that comes from QSFP+) into the DDR4 elements.
My plan is to integrate the Avalon FIFO Memory Intel FPGA IP with the PCIe DMA transfer example design for Windows (Provided in DE5a-Net CD/Demonstrations/PCIe_DDR4/) mention in the Chapter-7 (section 7.6 from page number 130) of the attached manual (DE5a-Net Arria 10 FPGA) DE5a-Net_User_Manual.pdf.
Any suggestion or documentation for an additional IP with an example design is most welcome.
PS: I am working in DE5a-Net-DDR4 Arria 10 GX (10 AX115N2F45E1SG) and use Quartus Prime Pro version 18.1
There is another thread that has been created with similar description on https://community.intel.com/t5/FPGA-Intellectual-Property/Integrating-a-Avalon-FIFO-IP-to-the-PCIe-DMA-transfer-example/m-p/1427485#M26591
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