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Ethernet data sniffing in FPGA

Dear all

I have MAX 10 development kit. I have to sniff the incoming  Ethernet packets in FPGA using MAC layer and I do not want to use TCP/IP stack in Nios II Processor. 

Please clarify and give me a idea how i can proceed.

Thank you in advance

Roopa

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Hi Roopa,


This is really depending on what design you would like to implement. If you are using Triple speed ethernet IP, it uses Avalon ST as the interface to the user logic. You may create your own logic to process the received packet via the Avalon ST interface of TSE IP.


Regards -SK


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If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 

 

Regards -SK

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