I have MAX 10 development kit. I have to sniff the incoming Ethernet packets in FPGA using MAC layer and I do not want to use TCP/IP stack in Nios II Processor.
Please clarify and give me a idea how i can proceed.
This is really depending on what design you would like to implement. If you are using Triple speed ethernet IP, it uses Avalon ST as the interface to the user logic. You may create your own logic to process the received packet via the Avalon ST interface of TSE IP.
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