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How OpenCL SDK memory access code is mapped to SDRAM ?

RElna
Beginner
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Hi,

I was wondering if someone can guide me on how opencl sdk operations are mapped to memory. For example, if we define a global buffer input data variable, would this be mapped to SDRAM or FPGA RAMs ?

 

Also, if it is mapped to SDRAM, which interconnect is used for the connection (e.g., FPGA-to-HPS SDRAM or FPGA-to HPS bridge ?

 

How can we differentiate and specify these connections ?

 

Thanks

Rana

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HRZ
Valued Contributor III
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Global buffers are mapped to the FPGA on-board DDR memory. All other buffers are mapped to either Block RAMs or registers depending on their size and access pattern.

 

Maybe someone else can answer your second question.

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RElna
Beginner
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Thanks for your reply. Can you guide me to a reference where I can read more about the mappings ? I have searched online a lot and I could not find a definite answer.

 

I also would like to know how to access HPS SDRAM from the opencl code.

 

 

 

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HRZ
Valued Contributor III
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