How OpenCL SDK memory access code is mapped to SDRAM ?

[RElna]

Hi,

I was wondering if someone can guide me on how opencl sdk operations are mapped to memory. For example, if we define a global buffer input data variable, would this be mapped to SDRAM or FPGA RAMs ?

Also, if it is mapped to SDRAM, which interconnect is used for the connection (e.g., FPGA-to-HPS SDRAM or FPGA-to HPS bridge ?

How can we differentiate and specify these connections ?

Thanks

Rana

[HRZ]

Global buffers are mapped to the FPGA on-board DDR memory. All other buffers are mapped to either Block RAMs or registers depending on their size and access pattern.

Maybe someone else can answer your second question.

[RElna]

Thanks for your reply. Can you guide me to a reference where I can read more about the mappings ? I have searched online a lot and I could not find a definite answer.

I also would like to know how to access HPS SDRAM from the opencl code.

[HRZ]

I remember the mapping was mentioned in the guides before but I cannot seem to find it anymore. You can check the following tutorial from Intel, though:

https://www.youtube.com/watch?v=1zGpN28mXN4

And the main OpenCL guides can be found here:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl-best-practices-guide.pdf

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/opencl-sdk/aocl_programming_guide.pdf