Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
464 Discussions

IP Cores required for generating programming file for PAC with Arria 10 GX FPGA


​I'm trying to synthesize my design for a PAC with Arria 10 GX FPGA. It seems the synthesis finishes fine, but the programming file isn't generated due to errors regarding expired IP licenses for the following IP cores:

  • PCIeOV with 4-PFs and 2K-VFs (6AF7 00FB)
  • Low Latency 10Gbps Ethernet MAC (6AF7 0119)
  • Low Latency 40Gbps Ethernet MAC and PHY (6AF7 011B)

One issue here is that the design doesn't use Ethernet at all, so I don't understand why the lack of license for the corresponding IP cores is even reported. I tried changing the default platform to both "a10_gx_pac_hssi" and "discrete_pcie3" (reported as existing on my machine by running "afu_platform_info -h") and the same behavior was repeated.

So my question is, are these IP cores required to be able to generate programming files for PAC with Arria 10 GX FPGA? If these are not required, then how can I resolve this error?


0 Kudos
0 Replies