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Intel MAX 10 FPGA 10M02SCE144I7G, RAM Inference issue

SVasi8
Beginner
605 Views

The following doesn't infer RAM:

Dummy_test_infer_RAM : single_port_ram GENERIC MAP(ADDR_WIDTH=> address_bits, DATA_WIDTH=>8) port map (we=> (PCI_CSx and not_R_W), clk =>clock,  addr=> dummy_addr , q => dummy_q, data => dummy_data);--

 

<< Tried synchronous and asynchronous RAM>>

-- q <= ram(addr_reg);-- location

It seams it infer the RAM if I set the file containing "single_port_ram" as Top-Level Entity, otherwise being called ("Dummy_test_infer_RAM :[…]" see above)

from the main file as Top-Level Entity, it doesn't infer.

 

 

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.std_logic_unsigned.all;

entity single_port_ram is

 generic

 (

  DATA_WIDTH : natural := 8;

  ADDR_WIDTH : natural := 6

 );

 port

 (

  clk  : in std_logic;

  addr : in natural range 0 to 2**ADDR_WIDTH - 1;

  data : in std_logic_vector((DATA_WIDTH-1) downto 0);

  we  : in std_logic := '1';

  q  : out std_logic_vector((DATA_WIDTH -1) downto 0)

 );

end entity;

architecture rtl of single_port_ram is

 

 -- Build a 2-D array type for the RAM

 subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0);

 type memory_t is array((2**ADDR_WIDTH)-1 downto 0) of word_t;

 -- Declare the RAM signal. 

 signal ram : memory_t;

 attribute ramstyle : string;

 attribute ramstyle of ram : signal is "MLAB, no_rw_check";--MLAB

 attribute max_depth : natural;

 attribute max_depth of ram : signal is 1024;

 -- Register to hold the address

 signal addr_reg : natural range 0 to 2**ADDR_WIDTH-1;

 

 --set_instance_assignment -name RAMSTYLE_ATTRIBUTE LOGIC -to ram;

 --set_global_assignment ram INFER_RAMS_FROM_RAW_LOGIC on;

-- (* ramstyle = "mlab" *) ram ;

--  (* max_depth = 512 *) reg [7:0] ram[0:63];

 

begin

 process(clk)

 begin

 if(rising_edge(clk)) then

  if(we = '1') then

   ram(addr) <= data;

  else

  

    addr_reg <= addr;

 q <= ram(addr_reg);--

  end if;

  -- Register the address for reading

--  addr_reg <= addr;

-- q <= ram(addr_reg);--

 end if;--if(rising_edge(clk)) then

 end process;

-- q <= ram(addr_reg);--

end rtl;

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

package single_port_ram_package is

 component single_port_ram

 

 generic

 (

  DATA_WIDTH : natural := 8;

  ADDR_WIDTH : natural := 6

 );

 port

 (

  clk  : in std_logic;

  addr : in natural range 0 to 2**ADDR_WIDTH - 1;

  data : in std_logic_vector((DATA_WIDTH-1) downto 0);

  we  : in std_logic := '1';

  q  : out std_logic_vector((DATA_WIDTH -1) downto 0)

 );

 end component;

end single_port_ram_package;

0 Kudos
10 Replies
RichardTanSY_Intel
416 Views

Hi,

I am not able to find information related to this error and could not duplicate the error as well.

Could you help to share the project that could duplicate this error? A simplified project will do.

SVasi8
Beginner
416 Views
Hi Richard, Please see attached a simplified version. Since then I found that “true_dual_port_ram_single_clock” does infer, but still it looks as the RAM doesn’t work. I have replaced for synchronous and a- synchronous version q_b <= ram(addr_reg_b); with q_b<= x"AA"; and does read out, so seems that the MUX and signals to read out works. Thanks, Regards, Stel
SVasi8
Beginner
416 Views
Hi, Any feedback on this? Thanks, Regards, Stel
SVasi8
Beginner
416 Views
Hi Richard, Did I send this info to the right place? Thanks, Regards, Stel
RichardTanSY_Intel
416 Views

Sorry for the late response but I do not see any attached file. Could you share the file again?

SVasi8
Beginner
416 Views
Hi, See attached , Regards, Stel
SVasi8
Beginner
416 Views
Hi Richard, Any feedback on this? Thanks, Regards, Stel
SVasi8
Beginner
416 Views

Attached archived project file.

Thanks,

Regards,

Stel

RichardTanSY_Intel
416 Views

Hi,

I believe the reason behind it does not infer RAM is due to the ram style is different. The first design ram style you posted in forum is MLAB while the main_ram_test design attached ram style is M9K.

MAX10 device only supports M9K or LCs memory block type. To check what type of memory block type is supported, you can go to IP Catalog, find and select RAM: 1-port IP then you can see the memory block type options that are available(supported).

SVasi8
Beginner
416 Views

Hi,

thanks for the answer. I have tried M9K and others.

Regards,

Stel

Reply