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Manually compiling aoc 17.1 generated RTL using quartus

Hi,

 

I have some opencl code which works perfectly fine (both in emulation and on FPGA) when compiled using aoc 17.1 compiler on VLAB. Now, I want to take the generated RTL from aoc and compile it manually. This is how I am trying to do this:

 

# Go to the build directory generated by aoc  % cd build  # manually execute run.sh % ./run.sh

However, this gives me the following error:

 

Error: Failed to synthesize partition Info: Saving post-synthesis snapshots for 1 partition(s) Error: Quartus Prime Synthesis was unsuccessful. 1 error, 2352 warnings Error: Peak virtual memory: 47647 megabytes Error: Processing ended: Fri May 17 15:03:58 2019 Error: Elapsed time: 01:03:06 Error: Total CPU time (on all processors): 01:32:52 Info (19538): Reading SDC files took 00:14:21 cumulatively in this process. ------------------------------------------------ ERROR: Error(s) found while running an executable. See report file(s) for error message(s). Message log indicates which executable was run last.   while executing "execute_module -dont_export_assignments -tool syn" (procedure "synthesize_persona_impl" line 14) invoked from within "synthesize_persona_impl $synth_rev" (procedure "compile_pr_revision" line 18) invoked from within "compile_pr_revision $options(impl)" (procedure "main" line 110) invoked from within "main" invoked from within "if {($::quartus(nameofexecutable) == "quartus") || ($::quartus(nameofexecutable) == "quartus_pro") || ($::quartus(nameofexecutable) == "qpro")} {   #..." (file "a10_partial_reconfig/flow.tcl" line 1039) ------------------------------------------------ Error (23031): Evaluation of Tcl script a10_partial_reconfig/flow.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 7 errors, 2352 warnings Error: Peak virtual memory: 789 megabytes Error: Processing ended: Fri May 17 15:04:12 2019 Error: Elapsed time: 01:06:08 Error: Total CPU time (on all processors): 01:35:50 ERROR: pll timing script failed.

Any suggestions on how to fix this?

 

Thanks,

Nitish

 

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2 Replies
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Hi Nitish, May I know what is VLAB ? Users are not expected to manually compile the OpenCL compiler generated files in Quartus. Please use OpenCL compiler to generate the bit streams. You might want to consider the HLS compiler if you intend to generate the RTL and manually compile files in Quartus. https://www.intel.com/content/www/us/en/software/programmable/quartus-prime/hls-compiler.html Thanks, Arslan
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Novice
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Hi Arslan,

 

This this Intel server + FPGA cluster (https://wiki.intel-research.net/FPGA.html#working-with-opencl). I know that we are not expected to compile the Opencl compiler generated files manually using Quartus, but I still want to do that for some research project.

 

Thanks,

Nitish

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