I am implementing shift register design in Intel OpenCL. So I am currently able to generate shift register hardware, but I need some clarification on how to realize shift register.
- How to decide shift register size?
- When I shifting from LSB to MSB, and I am trying to access all the elements , it get converted to register, but if I try to access few elements that from even not from the lsb, but any other index, I get shift register. Can anyone clarify ways to efficiently access shift register data points?
Here is my shift register implementation:
#define sr_size = 48
for(int y=0;y<11;y++)
{
#pragma unroll
for(int i=0;i<sr_size;i++)
{
inp[i]= 0.0f;
}
#pragma unroll
for(int i=sr_size-1;i>0;i--)
{
inp[i]= inp[i-1];
}
inp[sr_size-1] = input[ index];
#pragma unroll
for(int i=0;i<3;i++)
{
#pragma unroll
for(int j=0;j<3;j++)
{
dat[0] += inp[i+3];
dat[1] += inp[i+4];
dat[2] += inp[i+5];
dat[3] += inp[i+6];
dat[4] += inp[i+7];
dat[5] += inp[i+8];
}
}
}
}
This is converted to shift register because I use indexes i+3 onwards, but if I try to access index i it is not inferred to as shift register , I need help with that issue.
