IXGBE PHY register descriptions for Intel Ethernet Controller X552

[GKang7]

Hi,

We're currently using the XeonD 1539 SOC w/ built-in support for 10GBaseKR. For the 10GBaseKR interfaces, we're currently using the ixgbe device driver (v 5.6.3).

We're currently trying to disable Link Training by updating the IXBE_KRM_RX_TRN_LINKUP_CTRL register w/ IXGBE_KRM_TRN_LINKUP_CTRL_PROTOCOL_BYPASS enabled in ixgbe_setup_kr_speed_x550em (see ixgbe_x550.c):

/*** Added at the end of ixgbe_setup_kr_speed_x550em before call to ixgbe_restart_an_internal_phy_x550em ***/   /*** Disable/bypass Link Training ***/ status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, &reg_val); if (status != IXGBE_SUCCESS) { return status; } reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); if (status != IXGBE_SUCCESS) { printk("Error could not bypass link training\n"); return status; }

A couple of questions:

1) Does this sound like a reasonable approach to disable Link Training for 10GBaseKR PHY?

2) Is there documentation/data sheets that describes IXBE_KRM_RX_TRN_LINKUP_CTRL and other PHY registers in more detail? We've already looked at the XeonD-1500 and the Ethernet X550 data sheets but had no luck finding IXBE_KRM_RX_TRN_LINKUP_CTRL.

Thanks,

Gene

[Mike_Intel]

Hello GKang7,

Thank you for posting in Intel Ethernet Communities. 

For me to better understand the issue and assist you further, I need to gather the following details first.

1. What is the OS?
2. Are you designing a system or a board since you are using a 10GBaseKR PHY?

If you have questions, please let us know.

Best regards,

Michael L.

Intel Customer Support Technicians

A Contingent Worker at Intel

[GKang7]

Hi Michael,

Here's some answers to your questions: 

1) RHEL 7.7

2) Yes, we're integrating a single-board-computer with the XeonD-1539 SOC with built-in support for 10GBaseKR.   One of our link partners isn't completely compliant to 10GBaseKR so we're interested in disabling some features of the PHY (e.g. link training, auto-negotiation). From inspection of the ixgbe source code we've found some examples (see 1st message) but we'd like more information regarding these specific PHY registers.

[Mike_Intel]

Hello GKang7,

Base on your inquiry, we have specific forum for these issues and I will be transferring this thread for faster response.

If you have questions, please let us know.

Best regards,

Michael L.

Intel Customer Support Technicians

A Contingent Worker at Intel

[CarlosAM_INTEL]

Hello, @GKang7​:

Thank you for contacting Intel Embedded Community.

Could you please tell us if the affected designs have been designed by you or by a third-party company? In case that they are third-party units please give the part number, model, name of the manufacturer, where it is stated the information related to it. In case that it is your design, could you please clarify it has been reviewed by Intel and the list the sources that you have used to develop it?

We are waiting for your reply.

Best regards,

@Mæcenas_INTEL​.