Configuring OSC_CLK_OUT_1 pin on E3940 CPU

[DMora4]

Hello,

For a camera module with an IMX274 sensor that we want to use with our Apollo Lake board, I need to enable clock output on OSC_CLK_OUT_1 pin (pin number AF61) and set it to 24 MHz. As far as we can see on the oscilloscope, currently it is a constant 0. How do I do that? We are fine with configuring the pin from ACPI or from a Linux driver.

CPU Datasheet volume 1 557555 says that this is possible, but not how; from the "GPIO Multiplexing" chapter I can see that I don't need to change the pin function, but it doesn't say how to configure the (default) function.

I've found ACPI camera example in document 559811 chapter 7.6.1, but again it is not clear how to configure the clock.

Thanks in advance for any reply,

Dubravko

[CarlosAM_INTEL]

​Hello, @DMora4​:

Thank you for contacting Intel Embedded Community.

Could you please clarify if the design related to this thread has been developed by you or by a third-party company? In case that it is a third-party implementation please give us the part number. model, manufacturer name , and where is stated the information related to it.

Waiting for your clarification.

Best regards,

@Mæcenas_INTEL​.

[DMora4]

Hello Maecenas,

This design has been developed by us. I can ask if I can provide you the schematic, if you need it. As far as I know, there are not yet any publicly available documents. The product is briefly mentioned here: link (announcement for some upcoming workshops)

Our hardware team instructs me the CPU shall be identified close enough by the model name, Atom E3940. For the moment, we only want to configure clock output on OSC_CLK_OUT_1.

Best regards,

Dubravko

[CarlosAM_INTEL]

Hello, @DMora4​ :

Thanks for your reply.

The information that may answer your question is stated in section 10.1.20, on page 1004 of the Apollo Lake SoC External Design Specification (EDS) Volume 2 of 4 document # 557556. This document can be found when you are logged into your Resource & Design Center (RDC) privileged account at the following website:

http://www.intel.com/cd/edesign/library/asmo-na/eng/557556.htm

The RDC Account Support form is the channel to process your account update request. It can be found at:

https://www.intel.com/content/www/us/en/forms/design/contact-support.html

Best regards,

@Mæcenas_INTEL​.

[DMora4]

Thank you Maecenas,

This is exactly the information we need. It would seem we just need to toggle one bit in the register you've pointed out.

Best regards,

Dubravko

[CarlosAM_INTEL]

Hello, @DMora4​:

Thanks for your reply.

We are glad that the provided information has answered your questions.

Please do not hesitate to contact us again if you have more questions related to Intel Embedded products.

Best regards,

@Mæcenas_INTEL​.

[DMora4]

Hello Maecenas,

Unfortunately we need more help... we are familiar with some ARM processors, but not (yet) with x86/x64. We are having trouble figuring out how to access registers in IUNIT_CFG, as decribed in document 557556.

It looks to us like we are not supposed to set them directly, but instead write a camera declaration in ACPI and then an Intel's driver will read that at OS startup and initialize CPU registers appropriately? So according to document 559811 chapter 7.6.1, we should set:

• MCLK master clock in Hz, in SSDB structure
• M_CLK in SSDB structure - should we set this to 1 if we need OSC_CLK_OUT1 pin?
• DSDT_CAM_SNSR_MCLK in _DSM - is this the same as M_CLK in SSDB?
• do we need to set anything else to some specific values, for example Device function or Control logic id in SSDB?

Could you please confirm that we are on the right track, or if not advise a better way to proceed?

Best regards,

Dubravko

[CarlosAM_INTEL]

Hello, @DMora4​:

Thanks for your update.

We suggest you review the documents stated in the following website:

https://software.intel.com/en-us/articles/intel-sdm

By the way, as a reference please review the information stated at the following website:

http://rweverything.com/

Best regards,

@Mæcenas_INTEL​.