e3950 with DDR4 stuck on boot

[ChipsetWr]

We are developing our own Atom e3950-based platform. It uses DDR4 (4 chips MT53B256M32D1NP) memory down implementation (without SPD chip). We received test firmware from AMI (Aptio 5 UEFI), that outputs some debug data from UART and stucks in a dead loop. We assume this is the memory problem because of MRC errors. We cannot understand if this is a firmware (wrong memory settings for example) or hardware problem (may be bad soldering quality). AMI support says that this debug output and error messages are presumably from FSP/MRC part. Can you confirm that and if it is then what these errors and codes denote?

[ChipsetWr]

Ok, I've managed to fix MRC error - the problem was in memory settings (device width was incorrect), but still it dies after "CP A5" debug message.

Where can I find definition of Apollo Lake debug UART messages?

[Alberto_Sykes]

ChipsetWr, Thank you for posting in the Intel® Communities Support.

In reference to your inquiry, in order for us to be able to provide the most accurate assistance on this matter, I will move your thread to the proper department, which is "Embedded Intel Atom® Processors", they will further assist in there with your questions and further details about this topic:

https://community.intel.com/t5/Embedded-Intel-Atom-Processors/bd-p/embedded-atom-processors 

Regards,

Albert R.

Intel Customer Support Technician

A Contingent Worker at Intel

[CarlosAM_INTEL]

Hello, @ChipsetWr:

Thank you for contacting Intel Embedded Community.

You should verify that your assembly process fulfills the requirements stated in modules 3 and 5, on pages 20 through 34, and 68 through 76 of the  Manufacturing with the Intel Mobile Products Apollo Lake Intel Pentium and Celeron N and J Series Processors and Intel Atom Processor E3900 and A3900 Series document # 561676. Also, please review that your design has been developed following the recommendations stated in section 5.4, on pages 103 through 115 of the Intel® Pentium® and Celeron® Processor N- and J- Series (Formerly Apollo Lake) Platform Design Guide document # 557775. You can find these documents when you are logged into your  Resource and Design Center (RDC) privileged account on the following websites:

https://cdrdv2.intel.com/v1/dl/getContent/561676

https://cdrdv2.intel.com/v1/dl/getContent/557775

You should fill out the form stated on the following website when you have problems with the provided websites or want to update your RDC account:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

[ChipsetWr]

@CarlosAM_INTEL , thank you for your reply. We were following these guides from the start and rechecked it once again - everything seems ok.

Could you please help with UART log decoding?

[CarlosAM_INTEL]

Hello, @ChipsetWr:

Thanks for your reply.

We suggest verifying with the assistance of your Intel BIOS vendor (IBv) that the affected design fulfills the requirements stated on page 71 of the  Intel Pentium and Celeron Processor N- and J- Series Formerly Apollo Lake Intel Architecture Firmware Specification Volume 1 of 2 BIOS Specification document # 559810 that may answer your last communication.  You can find this document when you are logged into your Resource and Design Center (RDC) privileged account on the following website:

https://cdrdv2.intel.com/v1/dl/getContent/559810

You should fill out the form stated on the following website when you have problems with the provided website or want to update your RDC account:

https://www.intel.com/content/www/us/en/forms/support/my-intel-sign-on-support.html

Best regards,

@CarlosAM_INTEL.

[ChipsetWr]

Now if I leave only CH0 rank 1 in configuration then boot process passes until it hits CP A9 message. Then Dead loop again (see attached log).

[CarlosAM_INTEL]

Hello, @ChipsetWr:

Thanks for your reply.

We suggest contacting your Intel Bios Vendor (IBV) to verify that the affected projects have the latest Memory Reference Code (MRC). In case you are using an outdated version, please update it, and let us know the results.  You need to request the latest version from your IBV.

Best regards,

@CarlosAM_INTEL.

[ChipsetWr]

I asked our IBV about MRC version, they didn't respond yet.

The attached log in my previous post shows this info:

MRC REVISION ID 0.56.41
+ MMRC REVISION ID 89.24

Is this the last revision?

[ChipsetWr]

Sorry, I just found out that I wrote wrong thing in the first post. We use LPDDR4, not DDR4!

[CarlosAM_INTEL]

Hello, @ChipsetWr:

Thanks for your reply.

The IBV should confirm the latest supported MRC.

We want to understand this situation in more details, so we need to address the following questions:

Could you please provide the name of the IBV?

Could you please attach pictures of the processors related to this situation, specifically of their top side markings?

Could you please let us know if this situation happens only with a specific kind of memory, or it happens with memories from different manufacturers or specifications?

Could you please inform the Operating System (OS) installed in the affected designs?

Could you please confirm if Intel has verified the affected design?

We are waiting for your answer.

Best regards,

@CarlosAM_INTEL.

[ChipsetWr · Accepted solution]

Ok, the problem is kind of solved.

1. IBV provided BIOS with incorrect memory settings (DDR3L instead of LPDDR4, incorrect frequency/channel/rank config etc.)
2. There is some hardware problem on the mainboard - only 2 out of 4 memory chips were operational
3. The codes I asked about above denote stages of memory checking/training procedure performed by Intel FSP. The boot process was stalling because of reasons above.

What I found out:

booting process stalls on:

CP 00 - memory settings are unsupported by SoC/memory controller

CP A5 - faulty memory chips/incorrect channel/rank selection

CP A9 - DDR memory operational but unstable. We had to raise DDR voltage a bit to fix this issue