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CFL/PCH does not work after SLP_A#.


Hello. There.


I made my own board with COFFEE LAKE H.

If I had known the support page before, I would have requested circuit review or artwork review

First I made it based on my own datasheet.

I'll use the FPGA to directly adjust the PCH's power sequence.

While looking at the PDG document, I am writing the power sequence control in Verilog.

I am making a control program referring to the '45.4 Power Sequencing' item in the PDG document.

All of the VCCPRIM power is applied to the PCH, and both SLP_SUS# and SLP_A# come out normally. However, even after pressing the power button, SLP_S5# is always in assert state.

Of course it doesn't go to S4 and S3.

When I press PWRBTN for about 4 seconds, SLP_A# turns off and on, so PCH seems to work.

However, it does not work after S5#. 

Could it have something to do with the BIOS?

Both 'Figure 45-3' and 'Figure 45-4' in the '571391_CFL_H_PDG' document appear to access SPI FLASH after S5#.

I understood DSW_PWROK -> RSMRST -> PWRBTN -> S5#, but it stopped from S5#.

The assembled CPU is CL8068404165301S RFEJ and the PCH is FH82CM246 SR40E.

If the process does not work after SLP_A#, please review which part to check from.


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5 Replies

Hello, @lkk_vmetech:

Thank you for contacting Intel Embedded Community.

You need to verify that the affected design fulfills the SLP_A# requirements, which are stated in Tables 21-1, 33-5, 33-6, 33-8, 36-1, 45-1, and 45-5; in sections 33.5.1, 36.2.2, 36.2.7, 36.28, 36.2.19, and36.2.20, and; also in Figures 45-3 and 45-4, on pages 321, 378, 380, 381 425, 508, 522, 371, 426, 427, 429, , 513, and 515 of the Coffee Lake H Platform Design Guide (PDG) document # 571391. It can be found when you are logged into your Resource & Design Center (RDC) privileged account on the following website:


The RDC Account Support form is the channel to process your account update request or report any inconveniences with the provided site. It can be found at:


Best Regards,


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New Contributor I

Hello, @lkk_vmetech , @CarlosAM_INTEL 

I'm almost in the same situation. I have my own platform. And have the same problem at the beginning: no reaction to power button.

Of course I read PDG #571391. Also I have checked all power supplies of PCH. Everything correct. As you can see in diagram PCH seems alive, because it generates signals like SUSCLK, SLP_SUS#, SUSWARN# as expected. But in my case even SLP_A# is always asserted.

So my question to @lkk_vmetech: have you finished your project? Probably you have some advices what you've done.

Question to @CarlosAM_INTEL: before I pushed power button or assert WAKE# signal is it neccessary to have correct BIOS inside the SPI flash? I was trying checking with programmed flash and with empty flash. Difference I see by oscilloscope. In first case communication is about 175us, but with empty flash about 100us. But in both case no difference on reaction to power button or wake signals. Is there any role of the ME firmware at the beggining? I mean is the power button handled by ME? Could it be that problem is due to the incorrect BIOS firmware configuration?

Best regards,


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Hello, @vdpavel 


I will provide more information regarding your questions as soon as possible.


In the meantime, I would recommend that you submit your board details for a schematic and layout review on the following link to get a comprehensive examination: https://edc.intel.com/Tools/Design-Review/Default.aspx?language=en&r=944010280


Best Regards,




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New Contributor I

Hello, @Adolfo_S_Intel 


Thank you for your recommendation. I'd be glad to send my project for review, but it created in Altium Designer. Unfortunately, this CAD is not supported by Intel "Design Review Services".

Waiting for information.


Best regards,


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Hello @vdpavel 


According to the documentation from the Design Review Services webpage, they support Altium Designer .hyp format.


Best Regards,



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