Xeon-D 1500 CPU: state of the RAS_n/A16 pin during Row Address (RA) memory cycles

[CW4]

This question relates to the XEON-D 1500 CPU supporting 16Gb DDR4 memory in a down design. I understand from the CPU datasheet that the memory controller only supports 4Gb and 8Gb DDR4 densities in x4 and x8 data widths.

The DDR4 memory chip we are using in our design, Samsung K4AAG085WB-MCPB, is End Of Life (EOL). This is a 16Gb x8 Dual Die DDR4. The Dual Die is organized as two 8Gb DDR4 (1Gb x8) in parallel or two Ranks, where each Rank has a separate Chip Select. The Row Address for this device spans A[15:00].

Micron can offer a 32Gb DDR4, MT40A4G8NEA-062E:F, TwinDie 32Gb x8, organized as two 16Gb DDR4 (1Gb x16) in parallel or two Ranks. The Row Address for this device spans A[16:00]. We understand that populating the 32Gb DDR4 on our board will result in losing half of memory because the controller can only address 8Gb DDR4. However, my question to Intel is how does the Xeon-D 1500 memory controller drive the “RAS_n/A16” pin during Row Address (RA) ONLY. We cannot respin our PWB and are interested in populating the 32Gb TwinDie DDR4 in an 8Gb DDR4 PWB footprint.

From the JEDEC DDR4 Specification JESD79-4, pins RAS_n/A16, CAS_n/A15, WE_n/A14, are multiplexed by the memory controller and these pins are connected to the DDR4 and must be driven by the memory controller regardless of the memory size supported. However, these pins are driven differently based on the Row Address (RA). Since the Xeon-D 1500 CPU doesn’t support DDR4 larger than 8Gb, the RAS_n/A16 pin is essentially a “Don’t Care” during Row Address (RA); could be Low, High, Floating, or possibly change state when accessing the same address multiple times.

This is not an issue if the RAS_n/A16 pin remains static or flops at ‘different’ addresses. With a 16Gb DDR4, the memory controller will either read/write to upper 8Gb or lower 8Gb during RA. The real problem stems if the RAS_n/A16 pin should float or change state when accessing the ‘same’ address. Example: wrote to address 0xAAAA and RAS_n/A16 = 0, read from address 0xAAAA and RAS_n/A16 = 1. In this case the memory controller will be writing data to lower 8Gb but reading from upper 8Gb. So, the data will be non-contiguous. If the RAS_n/A16 pin should ever ‘float’ during RA, then it is unknown where the data will be.

Can Intel provide details on the Xeon-D 1500 memory controller when driving RAS_n/A16 pin during Row Address (RA) memory cycles? Additionally, does Intel have any other concerns controlling a 32Gb TwinDie DDR4 in a down design?

Thank you!

Barry Weinberger

[CarlosAM_INTEL]

Hello,  @CW4:

Thank you for contacting Intel Embedded Community.

We received your request but we want to address the following consultation to understand your request:

What is the part number of the Intel processor related to your request?

 We are waiting for your reply.

 Best regards,

@CarlosAM_INTEL.

[CW4]

Hi Carlos,

Thanks for your prompt reply!

There are several Xeon-D 1500 CPUs we use on different variants of our product.

However, they are within the same family and the part numbers are listed below;

• GG8067402569000 SR2DH - MPU XEON-D 1539 1.6Ghz 8C 35W
• GG8067402570403 SR2M1 - MPU XEON-D 1587 1.7Ghz 16C 65W
• GG8067402570801 SR2M5 - MPU XEON-D 1559 1.5Ghz 12C 45W
• GG8067402612700 SR2GF - MPU XEON-D 1537 1.7Ghz 8C 35W

I've also attached the datasheets for the DDR4 components;

• Samsung K4AAG085WB-MCRC (DDP 16Gb B-die DDR4) - EOL
• Micron MT40A4G8NEA-062E:F (32gb-ddr4-x4x8-2cs-twindie.pdf) - 32Gb Twindie DDR4
• Micron MT40A4G4 (16gb-ddr4-sdram.pdf) - 16Gb DDR4 used in TwinDie part

Hope this helps!

Best regards,

Barry

[CarlosAM_INTEL]

Hello, @CW4:

Thanks for your clarification.

We need to clarify that the Broadwell-DE processors have been discontinued and are no longer supported, as you may verify on the following website:

https://www.intel.com/content/www/us/en/support/articles/000022396/processors.html 

Also, you may find the available documentation for the Broadwell-DE processors on the following website:

https://www.intel.com/content/www/us/en/products/platforms/details/broadwell-de/docs.html

Best regards,
@CarlosAM_INTEL.

[CW4]

Hi Carlos,

Yes, I'm fully aware that the Broadwell-DE processors have been discontinued.
I have full access to all of the datasheets, Volumes 1-5.

However, Intel main support sent to this embedded forum for additional support.
Is there no Subject Matter Expert (SME) within Intel who can help answer my question?

Thank you!

Best regards,

Barry