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10-Gbps Ethernet MAC MegaCore control tx_crcins_control register access

Altera_Forum
Honored Contributor II
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I was trying to disable CRC insertion at MAC at TX side, but seems not able to access to "control tx_crcins_control" register inside MAC core (address 0x1080) with below command and simulation generate timeout.  

u_10g_drv.avalon_mm_csr_wr(32'h1080, 32'h0000_0001); //Disable to insert CRC at MAC Tx 

 

 

It seems this command has no effect to MAC, CRC still be inserted/appended to packet at MAC level that generate by testbench. I have tried to follow procedure to access this register as explain in "10-Gbps Ethernet MAC MegaCore Function User Guide", page 8-22 (item 4. MAC configuration register initialization) which recommend to disable tx and rx datapath before change configuration setting, but seem no effect. I also try to read this register, it shown message as timeout to get respond from this register.  

 

 

For your information, I have no problem when read or write other register, such as, tx_padins_control, rx_padcrc_control registers.
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