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Altera_Forum
Honored Contributor I
725 Views

IP Compiler

Hello to everyone,  

 

I would like to make a quesiton about the way the FIR II IP compiler should be used. I have read the documentation, and I have easily instantiated the FIR filter by using the FIR II Compiler from the plugin wizard. 

What I would like to do, is just to obtain a simple low pass filter, working on a digital signal with 12 bit samples at a speed of 600 MSPS. What is still not clear to me is, why when I set the input signal dimension to 12 bits, I get from the gui of the megacore that the output is about 34 bits? Is the first time that I am approaching to this IP and I am a little bit lost. 

 

I see that input and outputs of the block, are respectively 72 and 204 bits wide.....could someone give me a tip on how can I include this block into my design? For now I would be already grateful if I could run an easy FIR filter with the wanted behavior. Is there online any example or tutorial on how to use this block correctly? 

 

BR,  

Giovanni
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2 Replies
Altera_Forum
Honored Contributor I
26 Views

 

--- Quote Start ---  

Hello to everyone,  

 

I would like to make a quesiton about the way the FIR II IP compiler should be used. I have read the documentation, and I have easily instantiated the FIR filter by using the FIR II Compiler from the plugin wizard. 

What I would like to do, is just to obtain a simple low pass filter, working on a digital signal with 12 bit samples at a speed of 600 MSPS. What is still not clear to me is, why when I set the input signal dimension to 12 bits, I get from the gui of the megacore that the output is about 34 bits? Is the first time that I am approaching to this IP and I am a little bit lost. 

 

--- Quote End ---  

 

 

I haven't used FIR compiler but pretty familiar with DSPBuilder filters. Your speed of 600Msps can't be done in any FPGA I know. Hopefully a typo. 

 

Output bitgrowth follows sum f products of all coefficients and so grows accordingly(if your data is 12 bits and coeffs 12 bits then every product will have bitwidth of 24 bits and sum of two products will need 25bits and so on.) 

 

 

 

--- Quote Start ---  

 

I see that input and outputs of the block, are respectively 72 and 204 bits wide.....could someone give me a tip on how can I include this block into my design? For now I would be already grateful if I could run an easy FIR filter with the wanted behavior. Is there online any example or tutorial on how to use this block correctly? 

 

--- Quote End ---  

 

 

which block?
Altera_Forum
Honored Contributor I
26 Views

Hi Kaz,  

 

about the block, I was meaning the VHDL component generated by the IP Compiler, which looks like this: 

 

component FIR_stage_1 is 

port( 

clk : in std_logic := '0'; -- clk.clk 

reset_n : in std_logic := '0'; -- rst.reset_n 

ast_sink_data : in std_logic_vector(71 downto 0) := (others => '0'); -- avalon_streaming_sink.data 

ast_sink_valid : in std_logic := '0'; -- .valid 

ast_sink_error : in std_logic_vector(1 downto 0) := (others => '0'); -- .error 

ast_source_data : out std_logic_vector(203 downto 0); -- avalon_streaming_source.data 

ast_source_valid : out std_logic; -- .valid 

ast_source_error : out std_logic_vector(1 downto 0) -- .error 

); 

end component; 

 

Inside the FIR II Compiler I have defined an input bit width of 12 bits, but the avalon_sink_data input is 72 bits wide, for this I don´t understand how I should use the megacore to filter my signal. 

Unluckily I don´t have a license for the DSPBuilder, so I need to work just inside quartus and write down the code myself. 

 

About the signal´s speed, I was reading that the MLABs inside the Stratix IV 530 GX can work up to a maximum of 600 MHz, in past I have already experienced some issues while trying to realize a dual tone generatore on my chip.I would like to use FIR filters in order to realize a digital down converter.
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