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I am running in to an issue with debugging the E-Tile in 100G mode via the system console. Even though I have the "Enable JTAG to Avalon Master Bridge" option selected in the parameter editor, I am only seeing the serdes channels in the system console, not the MAC itself.
It's unclear if the problem is on the FPGA end (JTAG to Avalon master didn't get inserted as requested) or a problem on the system console end (didn't detect the MAC core).
Has anyone else run in to this issue? Are there any known workarounds?
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Hi Alex,
Good day.
Kindly try to check your MAC configuration through example design in AN647. I have attached the link for your reference. Try to compare the MAC configuration with your design.
Kindly download the example design and unarchive, there is a file called "config.tcl", this file contains the MAC register setting. System console will source this file to configure the MAC register.
And also kindly try to confirm whether this issue exist in design example. Design example will help to find the missing piece.
Regards,
Pavee
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Hi Alex,
Good day.
Any update from your end?
Regards,
Pavee
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I'm not sure what the relevance is of AN647, that's for a gigabit interface presumably using a soft MAC, and I'm trying to bring up a 100G interface with the E-tile hard MAC.
Anyway, checking with the E-tile example design is a good idea, I'll try that next week and report back if I'm seeing the same issue.
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Hi Alex,
Good day.
Hope the design example provide you some ideas. Any update?
Regards,
Pavee
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We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support.
If you have a new question, feel free to open a new thread to get the support from Intel experts.
Otherwise, the community users will continue to help you on this thread.
Thank you.

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