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100G Ethernet IP (Stratix 10) does not complete placement

JMiret
Novice
544 Views

Hi,

 

We're attempting to route a 100G interface with RS-FEC, using the Low Latency 100G IP. When we configure the IP without RS-FEC, it routes, but when we enable RS-FEC, it consistently fails to successfully place the design. When we disable RS-FEC, the design routes.

 

We suspect the problem relates to our SDC file, but we're not sure how to modify it. The current design only includes the 100G interface, with minimal logic to support ethernet control packets (and which has been validated to work over a 40G interface).

 

Are there additional constraints we should be looking at? 

I noticed that the user guide says that sometimes we may have to conduct floor planning - is that often the case?

 

0 Kudos
1 Solution
RichardTanSY_Intel
367 Views

Hi @JMiret 

 

Yup, it seems to be the case. In fact, I would recommend users to use the latest Quartus version 21.2 as we have fixed quite a few errors in the latest Quartus release.

With that, I believe your current issue has been resolved. Do you need further help in regards to this case? 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

 

View solution in original post

11 Replies
Deshi_Intel
Moderator
533 Views

HI,


  1. May I know are you encountering Quartus fitter compilation error ? What's the error message ?
  2. Which S10 Ethernet 100G IP that you are using ? H-tile hard IP ? E-tile hard IP or low latency 100G soft IP ?
  3. If you are using Hard IP then you may want to review the channel placement design requirement as RS_FEC is only available in certain channel only. Pls check out the respective Ethernet IP user guide doc to find out more info


If you are able to share your Quartus design QAR file here then I can help to review your design channel placement as well.

  • Just remove all your own sensitive user logic design and left with Ethernet 100G IP connection that able to reproduce the fitter error will do


Thanks.


Regards,

Deshi


JMiret
Novice
510 Views

Hello,

 

To answer your questions, and share some additional insight:

 

1) These errors are occurring with the Low Latency 100G soft IP, and

2) These errors ALSO occur with the Low Latency 40G soft IP,

3) They do not always occur. Right now, we get this error around 90% of the time. In some cases, the exact same build will sometimes work, but re-running the exact same build (using our automated CI system, so there is no human intervention, and the build environment is the same), causes the build to fail.

4) It doesn't seem to be related to complexity: when we try and compile the design with 100G only, we see this error, but we also see it when we take out our IP.

5) We know that our design routes, and the current build uses comparatively few resources.

6) These problems started occuring after we refactored the code - we suspect this caused a difference in how the inference engine is doing things - but the RTL viewer shows the code is mostly the same.

7) We have confirmed that this is an issue with Quartus 19.4, and Quartus 20.2.

Our latest build compiles if the IP is generated using Quartus 19.4, but the actual build is done by Quartus 20.2. If the entire build is carried out by Quartus 20.2, then we encounter the same issue.

 

The specific error message consists of a very large number of lines that look like this:

 

Info (170189): Fitter placement preparation operations beginning                                                                                                                                                                                                               
Info (170191): Fitter placement operations beginning                                                                                                                                                                                                                           
Error (170077): Cannot place the following nodes                                                                                                                                                                                                                               
   Error (170078): Cannot place node "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric_0|mm_interconnect_0|limiter_pipeline_001|gen_inst[0].core|data1[9]" of type Register cell with location constraints CUSTOM_REGION_X11_Y37_X282_Y432 from Promoted Clock Region File: /
1SX280HU3F50E2VG__/qdb/_compiler/blah/_flat/19.4.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_avalon_st_pipeline_
stage_1920/synth/altera_avalon_st_pipeline_base.v Line: 66                                                                                                                                                                                                                     
   Error (170079): Cannot place node "auto_fab_0|alt_sld_fab_0|alt_sld_fab_0|memfabric_0|mm_interconnect_0|rsp_mux|src_payload[2]~40xsyn" of type Combinational cell File: /scratch/fpga-q17/build-dir/fpga/build-tate/build__1SX280HU3F50E2VG__master__full40trx4__cyan-rtm2
.2-ddr-430-g2e4f3f99__2021-09-01-152714296614376/qdb/_compiler/tate/_flat/19.4.0/partitioned/1/.temp/sld_fabrics/ipgen/alt_sld_fab_0/alt_sld_fab_0/altera_merlin_multiplexer_191/synth/alt_sld_fab_0_altera_merlin_multiplexer_191_ldk5wsi.sv Line: 152

  

It includes DSP and ethernet blocks - but the issue we are seeing generally happens when both are in play. However, we've seen this failure when we compile with only usually works, however, if I include the Ethernet and our DSP blocks, it fails fitting.

 

If I compile a very, very, simple design, then it sometimes works. However, if I compile a design with additional user logic, I then get the errors above. We spent the day porting the code to quartus 20.2 from 19.4, but our CI system still shows these kind of errors. I've looked at the KB and forum posts, and it seems similar to the following:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/...

 

and

 

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Seeking-a-solution-to-Quartus-Prime-19-2...

 

In the second post, it suggests that this is an errata with Quartus itself. Can you confirm that there haven't been any similar issues in Quartus 20.2?

 

Best Regards,

 

 

 

 

 

JMiret
Novice
498 Views

I wanted to clarify the statistics above. I previously indicated that it occurred 90% of the time - that was incorrect. Since upgrading to Quartus 20.2, we now see this error around 5-10% of the time. This is on the exact same build, just being run multiple times.

Deshi_Intel
Moderator
481 Views

Hi,


Based on all your explanation so far + the symptom that SAME design sometime passed fitter compilation, sometime failed fitter compilation

  • I suspect this is likely due to your selected FPGA device core logic resource congestion issue
  • Then this has nothing to do with Ethernet IP functionality nor the Ethernet design itself, right ?
  • Sometime SDC constraint will affect the fitter placement result as well depends on how you constraint the clock/move the logic placement around.


You said that by creating smaller scale of design then it can passed fitter successfully, right ?

  • You can try debug experiment like use back your bigger design but purposely change to bigger FPGA device to test the fitter compilation. If fitter passed then you can be sure this is resource logic congestion issue
  • You can also view the Quartus "chip planner" in fitter passing design to see if your design is all concentrated in certain area of your FPGA device


Initially I pick up this case support due to we thought the issue is with Ethernet IP but now since this is related more on fitter compilation debug, then I will consult Intel internal team to see if I can get our Quartus software support agent to advise you further on fitter debug.


Thanks.


Regards,

dlim



JMiret
Novice
463 Views

I apologize; you're right. That may be the best course of action.

 

Another note: Moving to Quartus 20.2 has resulting in this error being much less frequent. We don't think this is a routing congestion issue, as the design is very much pipelined, and we are not close to fully utilization <10% on most figures, including DSP.

RichardTanSY_Intel
433 Views

Hi @JMiret 

 

I am Richard Tan and get to know that you need help in regards to the fitter issue.

From the discussion:

The errors 170078  indicate that the compiler had difficulties finding a legal placement solution for the design.  This may be caused by invalid location assignments, conflicting assignments, assigning nodes to incompatible physical locations on the device, not enough resources or hard-to-place Logic Lock regions. 

Action: Try to remove any invalid or conflicting assignments for the node. Also refer to the Fitter Floorplan view for overfilled regions on the device.

 

Whereas errors 170079 may be caused by not having enough resources or by hard-to-place Logic Lock regions that can interfere with the placement of this node.

Action: Try to choose a different seed value in Fitter Settings. If the design has Logic Lock regions, you can try to modify some of the Logic Lock regions.

 

Have you try to run the design in our latest Quartus version 21.2 and see if the issue still persist?

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

RichardTanSY_Intel
376 Views

Hi @JMiret ,

 

May I know does my latest reply help?

Have you try to run the design in our latest Quartus version 21.2 and see if the issue still persist?

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

JMiret
Novice
369 Views

Hi,

 

When running the identical design in Quartus 19 or 20, we would get the above errors - however, when using Quartus 21.2, we not seen any instance of these errors. Based on this, it looks like it was an error related to those versions of Quartus.

RichardTanSY_Intel
368 Views

Hi @JMiret 

 

Yup, it seems to be the case. In fact, I would recommend users to use the latest Quartus version 21.2 as we have fixed quite a few errors in the latest Quartus release.

With that, I believe your current issue has been resolved. Do you need further help in regards to this case? 

 

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

 

JMiret
Novice
342 Views

No, this fully addresses the issue. Thanks!

RichardTanSY_Intel
331 Views

I’m glad that your question has been addressed. With that, I will now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,
Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

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