i am using in my design (for Intel stratix 10 FPGA) a IP from Quartus 19.4 (but i see same behaviour also in 21.1 version) - Avalon-ST Intel Stratix 10 Hard IP for PCI Express .
we see the info from the bar_Range field but it seems to give wrong values - see attached picture.
we configure the BARs (base address registers for the bar ranges) but we see wrong values on this field.
we need assistance with this issue since it prevents us from using correctly all bars.
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