Bar range field not working correctly in Avalon-ST Intel Stratix 10 Hard IP for PCI Express

[ecohn]

hi,

i am using in my design (for Intel stratix 10 FPGA) a IP from Quartus 19.4 (but i see same behaviour also in 21.1 version)  - Avalon-ST Intel Stratix 10 Hard IP for PCI Express .

we see the info from the bar_Range field but it seems to give wrong values - see attached picture.

we configure the BARs (base address registers for the bar ranges) but we see wrong values on this field.

we need assistance with this issue since it prevents us from using correctly all bars.

thanks, 

Ehud

[KhaiChein_Y_Intel]

Hi,

Could you share the .ip file and what is the expected value?

Thanks

Best regadrs,

KhaiY

[KhaiChein_Y_Intel]

Hi,

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

Best regards,

KhaiY